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Commit 588f54f5 authored by Vladimir Bashkirtsev's avatar Vladimir Bashkirtsev
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Added support for Xilinx CPUs

parent 79e10382
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Makefile
View file @ 588f54f5
...@@ -39,3 +39,31 @@ gold: ...@@ -39,3 +39,31 @@ gold:
swapoff swap swapoff swap
rm -rf swap rm -rf swap
aarch64-none-elf:
tar xf binutils-2.36.1.tar.xz
mkdir binutils-build
cd binutils-build && ../binutils-2.36.1/configure --target=aarch64-none-elf --program-prefix=aarch64-none-elf- --prefix=$(CURDIR)/../toolchain/aarch64-none-elf --disable-nls --disable-werror
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/aarch64-none-elf
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/aarch64-none-elf install
rm -rf binutils-2.36.1
rm -rf binutils-build
arm-none-eabi:
tar xf binutils-2.36.1.tar.xz
mkdir binutils-build
cd binutils-build && ../binutils-2.36.1/configure --target=arm-none-eabi --program-prefix=arm-none-eabi- --prefix=$(CURDIR)/../toolchain/arm-none-eabi --disable-nls --disable-werror
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/arm-none-eabi
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/arm-none-eabi install
rm -rf binutils-2.36.1
rm -rf binutils-build
microblaze-xilinx-elf:
tar xf binutils-2.36.1.tar.xz
patch -Np1 -d binutils-2.36.1 < binutils-2.36.1-microblaze.patch
mkdir binutils-build
cd binutils-build && ../binutils-2.36.1/configure --target=microblaze-xilinx-elf --program-prefix=microblaze-xilinx-elf- --prefix=$(CURDIR)/../toolchain/microblaze-xilinx-elf --disable-nls --disable-werror
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/microblaze-xilinx-elf
$(MAKE) -C binutils-build tooldir=$(CURDIR)/../toolchain/microblaze-xilinx-elf install
rm -rf binutils-2.36.1
rm -rf binutils-build
binutils-2.36.1-microblaze.patch 0 → 100644
View file @ 588f54f5
diff -uNr binutils-2.36.1/bfd/bfd-in2.h binutils-2.36.1-microblaze/bfd/bfd-in2.h
--- binutils-2.36.1/bfd/bfd-in2.h 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/bfd/bfd-in2.h 2025-01-03 14:20:07.000000000 +0000
@@ -5438,10 +5438,15 @@
expressions of the form "Symbol Op Symbol" */
BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
-/* This is a 64 bit reloc that stores the 32 bit pc relative
+/* This is a 32 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). No relocation is
done here - only used for relaxing */
- BFD_RELOC_MICROBLAZE_64_NONE,
+ BFD_RELOC_MICROBLAZE_32_NONE,
+
+/* This is a 64 bit reloc that stores the 32 bit pc relative
+ * +value in two words (with an imm instruction). No relocation is
+ * +done here - only used for relaxing */
+ BFD_RELOC_MICROBLAZE_64_NONE,
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
diff -uNr binutils-2.36.1/bfd/elf32-microblaze.c binutils-2.36.1-microblaze/bfd/elf32-microblaze.c
--- binutils-2.36.1/bfd/elf32-microblaze.c 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/bfd/elf32-microblaze.c 2025-01-03 14:20:07.000000000 +0000
@@ -174,6 +174,20 @@
0x0000ffff, /* Dest Mask. */
FALSE), /* PC relative offset? */
+ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
+ 0, /* Rightshift. */
+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
+ 32, /* Bitsize. */
+ TRUE, /* PC_relative. */
+ 0, /* Bitpos. */
+ complain_overflow_bitfield, /* Complain on overflow. */
+ NULL, /* Special Function. */
+ "R_MICROBLAZE_32_NONE",/* Name. */
+ FALSE, /* Partial Inplace. */
+ 0, /* Source Mask. */
+ 0, /* Dest Mask. */
+ FALSE), /* PC relative offset? */
+
/* This reloc does nothing. Used for relaxation. */
HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
0, /* Rightshift. */
@@ -560,6 +574,9 @@
case BFD_RELOC_NONE:
microblaze_reloc = R_MICROBLAZE_NONE;
break;
+ case BFD_RELOC_MICROBLAZE_32_NONE:
+ microblaze_reloc = R_MICROBLAZE_32_NONE;
+ break;
case BFD_RELOC_MICROBLAZE_64_NONE:
microblaze_reloc = R_MICROBLAZE_64_NONE;
break;
@@ -1426,9 +1443,9 @@
relocation += addend;
relocation -= dtprel_base(info);
bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
- contents + offset + 2);
+ contents + offset + endian);
bfd_put_16 (input_bfd, relocation & 0xffff,
- contents + offset + 2 + INST_WORD_SIZE);
+ contents + offset + endian + INST_WORD_SIZE);
break;
case (int) R_MICROBLAZE_TEXTREL_64:
case (int) R_MICROBLAZE_TEXTREL_32_LO:
@@ -1844,8 +1861,7 @@
else
symval += irel->r_addend;
- if ((symval & 0xffff8000) == 0
- || (symval & 0xffff8000) == 0xffff8000)
+ if ((symval & 0xffff8000) == 0)
{
/* We can delete this instruction. */
sec->relax[sec->relax_count].addr = irel->r_offset;
@@ -1910,14 +1926,23 @@
}
break;
case R_MICROBLAZE_NONE:
+ case R_MICROBLAZE_32_NONE:
{
/* This was a PC-relative instruction that was
completely resolved. */
int sfix, efix;
+ unsigned int val;
bfd_vma target_address;
target_address = irel->r_addend + irel->r_offset;
sfix = calc_fixup (irel->r_offset, 0, sec);
efix = calc_fixup (target_address, 0, sec);
+
+ /* Validate the in-band val. */
+ val = bfd_get_32 (abfd, contents + irel->r_offset);
+ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+ }
+
irel->r_addend -= (efix - sfix);
/* Should use HOWTO. */
microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
@@ -1965,6 +1990,50 @@
irelscanend = irelocs + o->reloc_count;
for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
{
+ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
+ {
+ unsigned int val;
+
+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+
+ /* hax: We only do the following fixup for debug location lists. */
+ if (strcmp(".debug_loc", o->name))
+ continue;
+
+ /* This was a PC-relative instruction that was completely resolved. */
+ if (ocontents == NULL)
+ {
+ if (elf_section_data (o)->this_hdr.contents != NULL)
+ ocontents = elf_section_data (o)->this_hdr.contents;
+ else
+ {
+ /* We always cache the section contents.
+ Perhaps, if info->keep_memory is FALSE, we
+ should free them, if we are permitted to. */
+
+ if (o->rawsize == 0)
+ o->rawsize = o->size;
+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
+ if (ocontents == NULL)
+ goto error_return;
+ if (!bfd_get_section_contents (abfd, o, ocontents,
+ (file_ptr) 0,
+ o->rawsize))
+ goto error_return;
+ elf_section_data (o)->this_hdr.contents = ocontents;
+ }
+ }
+
+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
+
+ if (val != irelscan->r_addend) {
+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
+ }
+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
+
+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
+ irelscan->r_addend);
+ }
if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
{
isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
@@ -2024,7 +2093,7 @@
elf_section_data (o)->this_hdr.contents = ocontents;
}
}
- irelscan->r_addend -= calc_fixup (irel->r_addend
+ irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ isym->st_value,
0,
sec);
diff -uNr binutils-2.36.1/bfd/libbfd.h binutils-2.36.1-microblaze/bfd/libbfd.h
--- binutils-2.36.1/bfd/libbfd.h 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/bfd/libbfd.h 2025-01-03 14:20:07.000000000 +0000
@@ -2971,6 +2971,7 @@
"BFD_RELOC_MICROBLAZE_32_ROSDA",
"BFD_RELOC_MICROBLAZE_32_RWSDA",
"BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+ "BFD_RELOC_MICROBLAZE_32_NONE",
"BFD_RELOC_MICROBLAZE_64_NONE",
"BFD_RELOC_MICROBLAZE_64_GOTPC",
"BFD_RELOC_MICROBLAZE_64_GOT",
diff -uNr binutils-2.36.1/bfd/reloc.c binutils-2.36.1-microblaze/bfd/reloc.c
--- binutils-2.36.1/bfd/reloc.c 2021-01-13 08:17:12.000000000 +0000
+++ binutils-2.36.1-microblaze/bfd/reloc.c 2025-01-03 14:20:07.000000000 +0000
@@ -6893,6 +6893,12 @@
This is a 32 bit reloc for the microblaze to handle
expressions of the form "Symbol Op Symbol"
ENUM
+ BFD_RELOC_MICROBLAZE_32_NONE
+ENUMDOC
+ This is a 32 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction). No relocation is
+ done here - only used for relaxing
+ENUM
BFD_RELOC_MICROBLAZE_64_NONE
ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
diff -uNr binutils-2.36.1/binutils/readelf.c binutils-2.36.1-microblaze/binutils/readelf.c
--- binutils-2.36.1/binutils/readelf.c 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/binutils/readelf.c 2025-01-03 14:20:07.000000000 +0000
@@ -13852,6 +13852,10 @@
|| reloc_type == 32 /* R_AVR_DIFF32. */);
case EM_METAG:
return reloc_type == 3; /* R_METAG_NONE. */
+ case EM_MICROBLAZE:
+ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
+ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
+ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
case EM_NDS32:
return (reloc_type == 0 /* R_XTENSA_NONE. */
|| reloc_type == 204 /* R_NDS32_DIFF8. */
diff -uNr binutils-2.36.1/gas/config/tc-microblaze.c binutils-2.36.1-microblaze/gas/config/tc-microblaze.c
--- binutils-2.36.1/gas/config/tc-microblaze.c 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/gas/config/tc-microblaze.c 2025-01-03 14:20:07.000000000 +0000
@@ -37,6 +37,8 @@
#define OPTION_EB (OPTION_MD_BASE + 0)
#define OPTION_EL (OPTION_MD_BASE + 1)
+#define OPTION_LITTLE (OPTION_MD_BASE + 2)
+#define OPTION_BIG (OPTION_MD_BASE + 3)
void microblaze_generate_symbol (char *sym);
static bfd_boolean check_spl_reg (unsigned *);
@@ -755,7 +757,7 @@
if ((e->X_add_number >> 31) == 1)
e->X_add_number |= -((addressT) (1U << 31));
- if (e->X_add_number < min || e->X_add_number > max)
+ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
{
as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
(long) min, (long) max, (long) e->X_add_number);
@@ -915,7 +917,7 @@
unsigned reg2;
unsigned reg3;
unsigned isize;
- unsigned int immed, temp;
+ unsigned int immed, immed2, temp;
expressionS exp;
char name[20];
@@ -1176,7 +1178,76 @@
inst |= (reg2 << RA_LOW) & RA_MASK;
inst |= (immed << IMM_LOW) & IMM5_MASK;
break;
+ case INST_TYPE_RD_R1_IMM5_IMM5:
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
+ else
+ {
+ as_fatal (_("Error in statement syntax"));
+ reg1 = 0;
+ }
+ if (strcmp (op_end, ""))
+ op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
+ else
+ {
+ as_fatal (_("Error in statement syntax"));
+ reg2 = 0;
+ }
+
+ /* Check for spl registers. */
+ if (check_spl_reg (&reg1))
+ as_fatal (_("Cannot use special register with this instruction"));
+ if (check_spl_reg (&reg2))
+ as_fatal (_("Cannot use special register with this instruction"));
+
+ /* Width immediate value. */
+ if (strcmp (op_end, ""))
+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
+ else
+ as_fatal (_("Error in statement syntax"));
+ if (exp.X_op != O_constant)
+ {
+ as_warn (_("Symbol used as immediate width value for bit field instruction"));
+ immed = 1;
+ }
+ else
+ immed = exp.X_add_number;
+ if (opcode->instr == bsefi && immed > 31)
+ as_fatal (_("Width value must be less than 32"));
+
+ /* Shift immediate value. */
+ if (strcmp (op_end, ""))
+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
+ else
+ as_fatal (_("Error in statement syntax"));
+ if (exp.X_op != O_constant)
+ {
+ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
+ immed2 = 0;
+ }
+ else
+ {
+ output = frag_more (isize);
+ immed2 = exp.X_add_number;
+ }
+ if (immed2 != (immed2 % 32))
+ {
+ as_warn (_("Shift value greater than 32. using <value %% 32>"));
+ immed2 = immed2 % 32;
+ }
+ /* Check combined value. */
+ if (immed + immed2 > 32)
+ as_fatal (_("Width value + shift value must not be greater than 32"));
+
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+ inst |= (reg2 << RA_LOW) & RA_MASK;
+ if (opcode->instr == bsefi)
+ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
+ else
+ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
+ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
+ break;
case INST_TYPE_R1_R2:
if (strcmp (op_end, ""))
op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */
@@ -1854,6 +1925,8 @@
{
{"EB", no_argument, NULL, OPTION_EB},
{"EL", no_argument, NULL, OPTION_EL},
+ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
+ {"mbig-endian", no_argument, NULL, OPTION_BIG},
{ NULL, no_argument, NULL, 0}
};
@@ -2207,10 +2280,13 @@
/* This fixup has been resolved. Create a reloc in case the linker
moves code around due to relaxing. */
if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+ else if (fixP->fx_r_type == BFD_RELOC_32)
+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
else
fixP->fx_r_type = BFD_RELOC_NONE;
fixP->fx_addsy = section_symbol (absolute_section);
+ fixP->fx_done = 0;
}
return;
}
@@ -2431,6 +2507,7 @@
switch (fixp->fx_r_type)
{
case BFD_RELOC_NONE:
+ case BFD_RELOC_MICROBLAZE_32_NONE:
case BFD_RELOC_MICROBLAZE_64_NONE:
case BFD_RELOC_32:
case BFD_RELOC_MICROBLAZE_32_LO:
@@ -2508,9 +2585,11 @@
switch (c)
{
case OPTION_EB:
+ case OPTION_BIG:
target_big_endian = 1;
break;
case OPTION_EL:
+ case OPTION_LITTLE:
target_big_endian = 0;
break;
default:
@@ -2525,6 +2604,9 @@
/* fprintf(stream, _("\
MicroBlaze options:\n\
-noSmall Data in the comm and data sections do not go into the small data section\n")); */
+ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
+ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
+ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
}
diff -uNr binutils-2.36.1/gas/expr.c binutils-2.36.1-microblaze/gas/expr.c
--- binutils-2.36.1/gas/expr.c 2021-01-09 10:47:33.000000000 +0000
+++ binutils-2.36.1-microblaze/gas/expr.c 2025-01-03 14:20:07.000000000 +0000
@@ -803,6 +803,15 @@
break;
}
}
+ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
+ {
+ input_line_pointer--;
+
+ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
+ ? 0 : 10,
+ expressionP);
+ break;
+ }
c = *input_line_pointer;
switch (c)
{
diff -uNr binutils-2.36.1/include/elf/microblaze.h binutils-2.36.1-microblaze/include/elf/microblaze.h
--- binutils-2.36.1/include/elf/microblaze.h 2021-01-09 10:47:34.000000000 +0000
+++ binutils-2.36.1-microblaze/include/elf/microblaze.h 2025-01-03 14:20:07.000000000 +0000
@@ -61,6 +61,7 @@
RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */
RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */
RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */
+ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
END_RELOC_NUMBERS (R_MICROBLAZE_max)
/* Global base address names. */
diff -uNr binutils-2.36.1/opcodes/microblaze-dis.c binutils-2.36.1-microblaze/opcodes/microblaze-dis.c
--- binutils-2.36.1/opcodes/microblaze-dis.c 2021-01-09 10:47:34.000000000 +0000
+++ binutils-2.36.1-microblaze/opcodes/microblaze-dis.c 2025-01-03 14:21:20.000000000 +0000
@@ -73,6 +73,18 @@
}
static char *
+get_field_imm5width (struct string_buf *buf, long instr)
+{
+ char *p = strbuf (buf);
+
+ if (instr & 0x00004000)
+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
+ else
+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
+ return p;
+}
+
+static char *
get_field_imm5 (struct string_buf *buf, long instr)
{
char *p = strbuf (buf);
@@ -427,6 +439,10 @@
/* For mbar 16 or sleep insn. */
case INST_TYPE_NONE:
break;
+ /* For bit field insns. */
+ case INST_TYPE_RD_R1_IMM5_IMM5:
+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1 (&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
+ break;
/* For tuqula instruction */
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (&buf, inst));
diff -uNr binutils-2.36.1/opcodes/microblaze-opc.h binutils-2.36.1-microblaze/opcodes/microblaze-opc.h
--- binutils-2.36.1/opcodes/microblaze-opc.h 2021-01-09 10:47:34.000000000 +0000
+++ binutils-2.36.1-microblaze/opcodes/microblaze-opc.h 2025-01-03 14:20:07.000000000 +0000
@@ -59,6 +59,9 @@
/* For mbar. */
#define INST_TYPE_IMM5 20
+/* For bsefi and bsifi */
+#define INST_TYPE_RD_R1_IMM5_IMM5 21
+
#define INST_TYPE_NONE 25
@@ -89,8 +92,11 @@
#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
/* New Mask for msrset, msrclr insns. */
@@ -101,7 +107,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 289
+#define MAX_OPCODES 301
struct op_code_struct
{
@@ -155,9 +161,11 @@
{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
@@ -174,9 +182,14 @@
{"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
{"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
{"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
@@ -226,18 +239,24 @@
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
{"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
+ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
{"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
+ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
{"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
+ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
{"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
+ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
{"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
+ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
{"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
+ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
@@ -402,6 +421,8 @@
{"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
{"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
+ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
+ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
{"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
{"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
@@ -424,5 +445,8 @@
#define MIN_IMM5 ((int) 0x00000000)
#define MAX_IMM5 ((int) 0x0000001f)
+#define MIN_IMM_WIDTH ((int) 0x00000001)
+#define MAX_IMM_WIDTH ((int) 0x00000020)
+
#endif /* MICROBLAZE_OPC */
diff -uNr binutils-2.36.1/opcodes/microblaze-opcm.h binutils-2.36.1-microblaze/opcodes/microblaze-opcm.h
--- binutils-2.36.1/opcodes/microblaze-opcm.h 2021-01-09 10:47:34.000000000 +0000
+++ binutils-2.36.1-microblaze/opcodes/microblaze-opcm.h 2025-01-03 14:20:07.000000000 +0000
@@ -29,17 +29,17 @@
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
/* 'or/and/xor' are C++ keywords. */
microblaze_or, microblaze_and, microblaze_xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
+ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
+ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
- shr, sw, swr, swx, lbui, lhui, lwi,
+ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
@@ -129,6 +129,7 @@
#define RB_LOW 11 /* Low bit for RB. */
#define IMM_LOW 0 /* Low bit for immediate. */
#define IMM_MBAR 21 /* low bit for mbar instruction. */
+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
#define RD_MASK 0x03E00000
#define RA_MASK 0x001F0000
@@ -141,6 +142,9 @@
/* Imm mask for mbar. */
#define IMM5_MBAR_MASK 0x03E00000
+/* Imm mask for extract/insert width. */
+#define IMM5_WIDTH_MASK 0x000007C0
+
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
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