Skip to content

GitLab

E
embeddedsw-xilinx
Commit e02bdd51 authored by Vladimir Bashkirtsev's avatar Vladimir Bashkirtsev
Browse files
Options

Added power management for all GEM and SPI controllers

parent 86640545
Hide whitespace changes
Inline Side-by-side
Showing with 236 additions and 33 deletions
embeddedsw-xilinx_v2023.2-iwaveg35m.patch
View file @ e02bdd51
diff -uNr embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt embeddedsw-xilinx_v2023.2-iwaveg35m/lib/bsp/standalone/src/CMakeLists.txt diff -uNr embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt embeddedsw-xilinx_v2023.2-iwaveg35m/lib/bsp/standalone/src/CMakeLists.txt
--- embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/bsp/standalone/src/CMakeLists.txt 2025-02-06 08:53:37.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/bsp/standalone/src/CMakeLists.txt 2025-03-14 03:13:32.000000000 +0000
@@ -9,13 +9,16 @@ @@ -9,13 +9,16 @@
find_package(Mem) find_package(Mem)
list(APPEND defs "#ifndef XMEM_CONFIG_H_\n") list(APPEND defs "#ifndef XMEM_CONFIG_H_\n")
...@@ -20,7 +20,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt embedd ...@@ -20,7 +20,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/bsp/standalone/src/CMakeLists.txt embedd
file(WRITE ${CMAKE_CURRENT_SOURCE_DIR}/common/xmem_config.h ${defs}) file(WRITE ${CMAKE_CURRENT_SOURCE_DIR}/common/xmem_config.h ${defs})
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh 2025-03-14 03:13:32.000000000 +0000
@@ -191,6 +191,7 @@ @@ -191,6 +191,7 @@
cp $WORKING_DIR/outbyte.c $BSP_DIR/libsrc/standalone/src/ cp $WORKING_DIR/outbyte.c $BSP_DIR/libsrc/standalone/src/
cp $BOARD_DIR/xcsudma_g.c $BSP_DIR/libsrc/csudma/src/ cp $BOARD_DIR/xcsudma_g.c $BSP_DIR/libsrc/csudma/src/
...@@ -31,7 +31,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh emb ...@@ -31,7 +31,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/copy_bsp.sh emb
cp ../misc/zcu102/a53/xipipsu_g.c $BSP_DIR/libsrc/ipipsu/src/ cp ../misc/zcu102/a53/xipipsu_g.c $BSP_DIR/libsrc/ipipsu/src/
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipipsu_g.c 2025-03-14 03:13:32.000000000 +0000
@@ -0,0 +1,65 @@ @@ -0,0 +1,65 @@
+ +
+/******************************************************************* +/*******************************************************************
...@@ -100,7 +100,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipips ...@@ -100,7 +100,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xipips
+}; +};
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters.h 2025-03-14 03:13:32.000000000 +0000
@@ -0,0 +1,1980 @@ @@ -0,0 +1,1980 @@
+#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#ifndef XPARAMETERS_H /* prevent circular inclusions */
+#define XPARAMETERS_H /* by using protection macros */ +#define XPARAMETERS_H /* by using protection macros */
...@@ -2084,7 +2084,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparam ...@@ -2084,7 +2084,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparam
+#endif /* end of protection macro */ +#endif /* end of protection macro */
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparameters_ps.h 2025-03-14 03:13:32.000000000 +0000
@@ -0,0 +1,381 @@ @@ -0,0 +1,381 @@
+/****************************************************************************** +/******************************************************************************
+* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
...@@ -2469,7 +2469,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparam ...@@ -2469,7 +2469,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/a53/xparam
+#endif /* protection macro */ +#endif /* protection macro */
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.txt 2025-03-14 03:13:32.000000000 +0000
@@ -0,0 +1,17 @@ @@ -0,0 +1,17 @@
+canps +canps
+coresightps_dcc +coresightps_dcc
...@@ -2490,8 +2490,8 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.tx ...@@ -2490,8 +2490,8 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/drivers.tx
+usbpsu +usbpsu
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj.c 2025-03-14 02:59:21.000000000 +0000
@@ -0,0 +1,591 @@ @@ -0,0 +1,631 @@
+/****************************************************************************** +/******************************************************************************
+* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2017 - 2022 Xilinx, Inc. All rights reserved.
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved. +* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
...@@ -2580,7 +2580,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2580,7 +2580,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ +
+ +
+ PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */ + PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
+ 39, /* Number of slaves */ + 44, /* Number of slaves */
+ +
+ NODE_OCM_BANK_0, + NODE_OCM_BANK_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE, + PM_SLAVE_FLAG_IS_SHAREABLE,
...@@ -2654,6 +2654,18 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2654,6 +2654,18 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ PM_SLAVE_FLAG_IS_SHAREABLE, + PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+ +
+ NODE_ETH_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_ETH_2,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_ETH_3,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_UART_0, + NODE_UART_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE, + PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
...@@ -2662,6 +2674,14 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2662,6 +2674,14 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ PM_SLAVE_FLAG_IS_SHAREABLE, + PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+ +
+ NODE_SPI_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_SPI_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_I2C_0, + NODE_I2C_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE, + PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */ + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
...@@ -2747,7 +2767,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2747,7 +2767,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ +
+/* Prealloc for psu_cortexa53_0 */ +/* Prealloc for psu_cortexa53_0 */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, + PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
+ 13, + 15,
+ NODE_DDR, + NODE_DDR,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
...@@ -2778,6 +2798,16 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2778,6 +2798,16 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+ +
+ NODE_SPI_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_SPI_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_I2C_0, + NODE_I2C_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
...@@ -2816,7 +2846,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2816,7 +2846,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ +
+ /* Prealloc for psu_cortexr5_0 */ + /* Prealloc for psu_cortexr5_0 */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, + PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+ 15, + 17,
+ NODE_TCM_0_A, + NODE_TCM_0_A,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
...@@ -2852,6 +2882,16 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -2852,6 +2882,16 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+ +
+ NODE_SPI_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_SPI_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_I2C_0, + NODE_I2C_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */ + PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */ + PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
...@@ -3085,7 +3125,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj ...@@ -3085,7 +3125,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/pm_cfg_obj
+#endif +#endif
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c 2025-03-14 03:13:32.000000000 +0000
@@ -0,0 +1,21155 @@ @@ -0,0 +1,21155 @@
+/****************************************************************************** +/******************************************************************************
+* +*
...@@ -24244,7 +24284,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c ...@@ -24244,7 +24284,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.c
+ +
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.c 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,21162 @@ @@ -0,0 +1,21162 @@
+/****************************************************************************** +/******************************************************************************
+* +*
...@@ -45410,7 +45450,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_g ...@@ -45410,7 +45450,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_g
+ +
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_gpl.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,35433 @@ @@ -0,0 +1,35433 @@
+/****************************************************************************** +/******************************************************************************
+* +*
...@@ -80847,7 +80887,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_g ...@@ -80847,7 +80887,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init_g
+#endif +#endif
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,35419 @@ @@ -0,0 +1,35419 @@
+/****************************************************************************** +/******************************************************************************
+* +*
...@@ -116270,7 +116310,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h ...@@ -116270,7 +116310,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/psu_init.h
+#endif +#endif
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu_g.c 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,65 @@ @@ -0,0 +1,65 @@
+ +
+/******************************************************************* +/*******************************************************************
...@@ -116339,7 +116379,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu ...@@ -116339,7 +116379,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xipipsu
+}; +};
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,1682 @@ @@ -0,0 +1,1682 @@
+/****************************************************************************** +/******************************************************************************
+* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved.
...@@ -118025,7 +118065,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparame ...@@ -118025,7 +118065,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparame
+#endif /* end of protection macro */ +#endif /* end of protection macro */
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparameters_ps.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,392 @@ @@ -0,0 +1,392 @@
+/****************************************************************************** +/******************************************************************************
+* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved. +* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
...@@ -118421,7 +118461,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparame ...@@ -118421,7 +118461,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/r5/xparame
+*/ +*/
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.c 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,30 @@ @@ -0,0 +1,30 @@
+ +
+/******************************************************************* +/*******************************************************************
...@@ -118455,7 +118495,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g. ...@@ -118455,7 +118495,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xcsudma_g.
+}; +};
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,78 @@ @@ -0,0 +1,78 @@
+/****************************************************************************** +/******************************************************************************
+* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
...@@ -118537,7 +118577,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c ...@@ -118537,7 +118577,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xsdps_g.c
+/** @} */ +/** @} */
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.c 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
+ +
+/******************************************************************* +/*******************************************************************
...@@ -118572,7 +118612,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g. ...@@ -118572,7 +118612,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/misc/g35m/xusbpsu_g.
+}; +};
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,949 @@ @@ -0,0 +1,949 @@
+/* +/*
+ * Si5341 Rev D Configuration Register Export Header File + * Si5341 Rev D Configuration Register Export Header File
...@@ -119525,7 +119565,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg. ...@@ -119525,7 +119565,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs1-reg.
+#endif +#endif
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h 1970-01-01 00:00:00.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h 1970-01-01 00:00:00.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.h 2025-03-14 03:13:33.000000000 +0000
@@ -0,0 +1,946 @@ @@ -0,0 +1,946 @@
+/* +/*
+ * Si5341 Rev D Configuration Register Export Header File + * Si5341 Rev D Configuration Register Export Header File
...@@ -120475,7 +120515,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg. ...@@ -120475,7 +120515,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/si5341b-cs2-reg.
+#endif +#endif
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c 2025-03-14 03:13:33.000000000 +0000
@@ -37,6 +37,15 @@ @@ -37,6 +37,15 @@
******************************************************************************/ ******************************************************************************/
/***************************** Include Files *********************************/ /***************************** Include Files *********************************/
...@@ -120856,7 +120896,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c em ...@@ -120856,7 +120896,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_board.c em
* This function does board specific initialization. * This function does board specific initialization.
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c 2025-03-14 03:13:33.000000000 +0000
@@ -62,10 +62,43 @@ @@ -62,10 +62,43 @@
u32 XFsbl_HookAfterBSDownload(void ) u32 XFsbl_HookAfterBSDownload(void )
{ {
...@@ -120901,9 +120941,17 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c em ...@@ -120901,9 +120941,17 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_fsbl/src/xfsbl_hooks.c em
return Status; return Status;
} }
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/drivers.txt embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/drivers.txt
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/drivers.txt 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/drivers.txt 2025-03-14 03:13:33.000000000 +0000
@@ -16,3 +16,4 @@
dpdma
dppsu
video_common
+spips
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/Makefile diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/Makefile
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/Makefile 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/Makefile 2025-03-14 03:13:33.000000000 +0000
@@ -1,6 +1,6 @@ @@ -1,6 +1,6 @@
# Makefile generated by Xilinx. # Makefile generated by Xilinx.
-COMPILER := mb-gcc -COMPILER := mb-gcc
...@@ -120915,8 +120963,128 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile embed ...@@ -120915,8 +120963,128 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/Makefile embed
PROCESSOR = psu_pmu_0 PROCESSOR = psu_pmu_0
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h 2025-03-14 03:13:33.000000000 +0000
@@ -1209,19 +1209,38 @@ @@ -460,7 +460,46 @@
#define XPAR_XDPPSU_0_BASEADDR 0xFD4A0000
#define XPAR_XDPPSU_0_HIGHADDR 0xFD4AFFFF
/* Definitions for driver EMACPS */
-#define XPAR_XEMACPS_NUM_INSTANCES 1
+#define XPAR_XEMACPS_NUM_INSTANCES 4
+
+/* Definitions for peripheral PSU_ETHERNET_0 */
+#define XPAR_PSU_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_0_BASEADDR 0xFF0B0000
+#define XPAR_PSU_ETHERNET_0_HIGHADDR 0xFF0BFFFF
+#define XPAR_PSU_ETHERNET_0_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 249975021
+
+/* Definitions for peripheral PSU_ETHERNET_1 */
+#define XPAR_PSU_ETHERNET_1_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_1_BASEADDR 0xFF0C0000
+#define XPAR_PSU_ETHERNET_1_HIGHADDR 0xFF0CFFFF
+#define XPAR_PSU_ETHERNET_1_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_1_ENET_TSU_CLK_FREQ_HZ 249975021
+
+/* Definitions for peripheral PSU_ETHERNET_2 */
+#define XPAR_PSU_ETHERNET_2_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_2_BASEADDR 0xFF0D0000
+#define XPAR_PSU_ETHERNET_2_HIGHADDR 0xFF0DFFFF
+#define XPAR_PSU_ETHERNET_2_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_2_ENET_TSU_CLK_FREQ_HZ 249975021
/* Definitions for peripheral PSU_ETHERNET_3 */
#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
@@ -478,13 +517,23 @@
/******************************************************************/
-#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_0_IS_CACHE_COHERENT 0
#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_0_REF_CLK 0xff
+#define XPAR_PSU_ETHERNET_1_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_1_REF_CLK 0xff
+#define XPAR_PSU_ETHERNET_2_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_2_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_2_REF_CLK 0xff
+#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_3_IS_CACHE_COHERENT 0
#define XPAR_PSU_ETHERNET_3_REF_CLK 0xff
-/* Canonical definitions for peripheral PSU_ETHERNET_3 */
-#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
-#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
-#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
+
+/* Canonical definitions for peripheral PSU_ETHERNET_0 */
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
+#define XPAR_XEMACPS_0_HIGHADDR 0xFF0BFFFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987511
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
@@ -493,6 +542,42 @@
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975021
+/* Canonical definitions for peripheral PSU_ETHERNET_1 */
+#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSU_ETHERNET_1_DEVICE_ID
+#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
+#define XPAR_XEMACPS_1_HIGHADDR 0xFF0CFFFF
+#define XPAR_XEMACPS_1_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_1_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_1_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_1_ENET_SLCR_10Mbps_DIV1 10
+#define XPAR_XEMACPS_1_ENET_TSU_CLK_FREQ_HZ 249975021
+/* Canonical definitions for peripheral PSU_ETHERNET_2 */
+#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PSU_ETHERNET_2_DEVICE_ID
+#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
+#define XPAR_XEMACPS_2_HIGHADDR 0xFF0DFFFF
+#define XPAR_XEMACPS_2_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_2_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_2_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_2_ENET_SLCR_10Mbps_DIV1 10
+#define XPAR_XEMACPS_2_ENET_TSU_CLK_FREQ_HZ 249975021
+/* Canonical definitions for peripheral PSU_ETHERNET_3 */
+#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
+#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
+#define XPAR_XEMACPS_3_HIGHADDR 0xFF0EFFFF
+#define XPAR_XEMACPS_3_ENET_CLK_FREQ_HZ 124987511
+#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_3_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_3_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_3_ENET_SLCR_10Mbps_DIV1 10
+#define XPAR_XEMACPS_3_ENET_TSU_CLK_FREQ_HZ 249975021
/******************************************************************/
@@ -1209,19 +1294,38 @@
/******************************************************************/ /******************************************************************/
/* Definitions for driver SDPS */ /* Definitions for driver SDPS */
...@@ -120960,7 +121128,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h ...@@ -120960,7 +121128,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h
#define XPAR_PSU_SD_1_CLK_50_SDR_ITAP_DLY 0x15 #define XPAR_PSU_SD_1_CLK_50_SDR_ITAP_DLY 0x15
#define XPAR_PSU_SD_1_CLK_50_SDR_OTAP_DLY 0x5 #define XPAR_PSU_SD_1_CLK_50_SDR_OTAP_DLY 0x5
#define XPAR_PSU_SD_1_CLK_50_DDR_ITAP_DLY 0x3D #define XPAR_PSU_SD_1_CLK_50_DDR_ITAP_DLY 0x3D
@@ -1232,17 +1251,19 @@ @@ -1232,17 +1336,19 @@
/******************************************************************/ /******************************************************************/
...@@ -120989,7 +121157,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h ...@@ -120989,7 +121157,7 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h
#define XPAR_XSDPS_0_HAS_EMIO 0 #define XPAR_XSDPS_0_HAS_EMIO 0
#define XPAR_XSDPS_0_SLOT_TYPE 3 #define XPAR_XSDPS_0_SLOT_TYPE 3
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0 #define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
@@ -1253,6 +1274,25 @@ @@ -1253,6 +1359,59 @@
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0x3 #define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0x3
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0x3 #define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0x3
...@@ -121011,20 +121179,55 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h ...@@ -121011,20 +121179,55 @@ diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/misc/xparameters.h
+#define XPAR_XSDPS_1_CLK_50_DDR_OTAP_DLY 0x4 +#define XPAR_XSDPS_1_CLK_50_DDR_OTAP_DLY 0x4
+#define XPAR_XSDPS_1_CLK_100_SDR_OTAP_DLY 0x3 +#define XPAR_XSDPS_1_CLK_100_SDR_OTAP_DLY 0x3
+#define XPAR_XSDPS_1_CLK_200_SDR_OTAP_DLY 0x3 +#define XPAR_XSDPS_1_CLK_200_SDR_OTAP_DLY 0x3
+
+
+/******************************************************************/
+
+/* Definitions for driver SPIPS */
+#define XPAR_XSPIPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PSU_SPI_0 */
+#define XPAR_PSU_SPI_0_DEVICE_ID 0
+#define XPAR_PSU_SPI_0_BASEADDR 0xFF040000
+#define XPAR_PSU_SPI_0_HIGHADDR 0xFF04FFFF
+#define XPAR_PSU_SPI_0_SPI_CLK_FREQ_HZ 199999985
+
+
+/* Definitions for peripheral PSU_SPI_1 */
+#define XPAR_PSU_SPI_1_DEVICE_ID 1
+#define XPAR_PSU_SPI_1_BASEADDR 0xFF050000
+#define XPAR_PSU_SPI_1_HIGHADDR 0xFF05FFFF
+#define XPAR_PSU_SPI_1_SPI_CLK_FREQ_HZ 199999985
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_SPI_0 */
+#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PSU_SPI_0_DEVICE_ID
+#define XPAR_XSPIPS_0_BASEADDR 0xFF040000
+#define XPAR_XSPIPS_0_HIGHADDR 0xFF04FFFF
+#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 199999985
+
+/* Canonical definitions for peripheral PSU_SPI_1 */
+#define XPAR_XSPIPS_1_DEVICE_ID XPAR_PSU_SPI_1_DEVICE_ID
+#define XPAR_XSPIPS_1_BASEADDR 0xFF050000
+#define XPAR_XSPIPS_1_HIGHADDR 0xFF05FFFF
+#define XPAR_XSPIPS_1_SPI_CLK_FREQ_HZ 199999985
+ +
/******************************************************************/ /******************************************************************/
diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/src/Makefile embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/src/Makefile diff -uNr embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/src/Makefile embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/src/Makefile
--- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/src/Makefile 2023-10-12 15:51:06.000000000 +0000 --- embeddedsw-xilinx_v2023.2/lib/sw_apps/zynqmp_pmufw/src/Makefile 2023-10-12 15:51:06.000000000 +0000
+++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/src/Makefile 2025-02-05 21:41:42.000000000 +0000 +++ embeddedsw-xilinx_v2023.2-iwaveg35m/lib/sw_apps/zynqmp_pmufw/src/Makefile 2025-03-14 03:17:29.000000000 +0000
@@ -1,7 +1,7 @@ @@ -1,7 +1,8 @@
# Auto Generated by Xilinx generate_app. Modify at your own risk # Auto Generated by Xilinx generate_app. Modify at your own risk
-CC := mb-gcc -CC := mb-gcc
-CC_FLAGS := -MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -CC_FLAGS := -MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul
+CC := microblaze-xilinx-elf-gcc +CC := microblaze-xilinx-elf-gcc
+CC_FLAGS := -MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -DENABLE_EM -DENABLE_SCHEDULER +CC_FLAGS := -Os -flto -ffat-lto-objects -MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -DENABLE_EM -DENABLE_SCHEDULER
+
CFLAGS := -Os -flto -ffat-lto-objects CFLAGS := -Os -flto -ffat-lto-objects
LN_FLAGS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilfpga,-lxilsecure,-lxilskey,-lxil,-lgcc,-lc,--end-group -nostartfiles -Wl,--gc-sections LN_FLAGS := -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilfpga,-lxilsecure,-lxilskey,-lxil,-lgcc,-lc,--end-group -nostartfiles -Wl,--gc-sections
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment