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Commit fca85a9a authored by Vladimir Bashkirtsev's avatar Vladimir Bashkirtsev
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Added support for Nile board with Orinoco Mini

parent 6d5edfac
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Makefile
View file @ fca85a9a
...@@ -336,6 +336,57 @@ iwaveg35m: ...@@ -336,6 +336,57 @@ iwaveg35m:
swapoff swap swapoff swap
rm -rf swap rm -rf swap
nileorinocomini-clfs:
dd if=/dev/zero of=swap bs=1048576 count=1024
chmod 600 swap
mkswap swap
swapon swap
tar xf linux-5.12.10.tar.xz
patch -Np1 -d linux-5.12.10 < linux-5.12.10-xilinx.patch
patch -Np1 -d linux-5.12.10 < linux-5.12.10-nileorinocomini.patch
$(MAKE) -C linux-5.12.10 zynqmp_nileorinocomini_defconfig
/kernelconfig/initramfs/prepare
bash -c 'files=`ls -1 /kernelconfig/nile-orinoco-mini` ; for config in $$files ; do cat /kernelconfig/nile-orinoco-mini/$$config >> linux-5.12.10/.config ; done'
$(MAKE) -C linux-5.12.10 oldconfig
$(MAKE) -C linux-5.12.10
$(MAKE) -C linux-5.12.10 install modules_install dtbs_install
cp -v linux-5.12.10/.config /boot/config-5.12.10
ln -svf vmlinux-5.12.10 /boot/Image
ln -svf dtbs/5.12.10/xilinx/nile-orinoco-mini.dtb /boot/machine.dtb
$(MAKE) -C ../kmod tests
rm -rf /kernelconfig
rm -rf linux-5.12.10
swapoff swap
rm -rf swap
nileorinocomini:
dd if=/dev/zero of=swap bs=1048576 count=1024
chmod 600 swap
mkswap swap
swapon swap
tar xf linux-5.12.10.tar.xz
patch -Np1 -d linux-5.12.10 < linux-5.12.10-xilinx.patch
patch -Np1 -d linux-5.12.10 < linux-5.12.10-nileorinocomini.patch
cp -v /boot/config-5.12.10 linux-5.12.10/.config
/kernelconfig/initramfs/prepare
bash -c 'files=`ls -1 /kernelconfig/nile-orinoco-mini` ; for config in $$files ; do cat /kernelconfig/nile-orinoco-mini/$$config >> linux-5.12.10/.config ; done'
$(MAKE) -C linux-5.12.10 oldconfig
$(MAKE) -C linux-5.12.10
rm -rf /lib/modules
rm -rf /boot/dtbs
rm -f /boot/config*
rm -f /boot/vmlinux*
rm -f /boot/System.map*
$(MAKE) -C linux-5.12.10 install modules_install dtbs_install
cp -v linux-5.12.10/.config /boot/config-5.12.10
ln -svf vmlinux-5.12.10 /boot/Image
ln -svf dtbs/5.12.10/xilinx/nile-orinoco-mini.dtb /boot/machine.dtb
rm -f /boot/*.old
rm -rf /kernelconfig
rm -rf linux-5.12.10
swapoff swap
rm -rf swap
rpi3b-clfs: rpi3b-clfs:
dd if=/dev/zero of=swap bs=1048576 count=1024 dd if=/dev/zero of=swap bs=1048576 count=1024
chmod 600 swap chmod 600 swap
......
build.xml
View file @ fca85a9a
...@@ -126,6 +126,10 @@ CONFIG_CROSS_COMPILE="${CLFS_TARGET}" ...@@ -126,6 +126,10 @@ CONFIG_CROSS_COMPILE="${CLFS_TARGET}"
<ant antfile="packages/linux/build.xml" target="boot-linux-armv8"/> <ant antfile="packages/linux/build.xml" target="boot-linux-armv8"/>
</target> </target>
<target name="boot-linux-nile-orinoco-mini">
<ant antfile="packages/linux/build.xml" target="boot-linux-armv8"/>
</target>
<target name="boot-linux-raspberry-pi-3-b"> <target name="boot-linux-raspberry-pi-3-b">
<ant antfile="packages/linux/build.xml" target="boot-linux-armv8"/> <ant antfile="packages/linux/build.xml" target="boot-linux-armv8"/>
</target> </target>
......
linux-5.12.10-nileorinocomini.patch 0 → 100644
View file @ fca85a9a
diff -uNr linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/Makefile linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/Makefile
--- linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/Makefile 2025-03-25 02:39:08.000000000 +0000
+++ linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/Makefile 2025-03-28 00:20:30.000000000 +0000
@@ -20,3 +20,6 @@
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu1285-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu208-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu216-revA.dtb
+
+# Nile board with Orinoco Mini
+dtb-$(CONFIG_ARCH_ZYNQMP) += nile-orinoco-mini.dtb
diff -uNr linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/nile-orinoco-mini.dts linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/nile-orinoco-mini.dts
--- linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/nile-orinoco-mini.dts 1970-01-01 00:00:00.000000000 +0000
+++ linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/nile-orinoco-mini.dts 2025-03-28 00:11:03.000000000 +0000
@@ -0,0 +1,439 @@
+/dts-v1/;
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &spi0;
+ mdio-gpio0 = &mdio_gpio;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x0 0x7ff00000>,
+ <0x00000008 0x00000000 0x0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ rpu0vdev0vring0: rpu0vdev0vring0@70040000 {
+ no-map;
+ reg = <0x00 0x70040000 0x00 0x4000>;
+ };
+
+ rpu0vdev0vring1: rpu0vdev0vring1@70044000 {
+ no-map;
+ reg = <0x00 0x70044000 0x00 0x4000>;
+ };
+
+ rpu0vdev0buffer: rpu0vdev0buffer@70048000 {
+ no-map;
+ reg = <0x00 0x70048000 0x00 0x100000>;
+ };
+
+ rproc: rproc@70000000 {
+ no-map;
+ reg = <0x00 0x70000000 0x00 0x40000>;
+ };
+ };
+
+ tcm_0a: tcm_0a@ffe00000 {
+ no-map;
+ reg = <0x00 0xffe00000 0x00 0x10000>;
+ status = "okay";
+ compatible = "mmio-sram";
+ power-domain = <&zynqmp_firmware 0x0f>;
+ };
+
+ tcm_0b: tcm_0b@ffe20000 {
+ no-map;
+ reg = <0x00 0xffe20000 0x00 0x10000>;
+ status = "okay";
+ compatible = "mmio-sram";
+ power-domain = <&zynqmp_firmware 0x10>;
+ };
+
+ rf5ss@ff9a0000 {
+ compatible = "xlnx,zynqmp-r5-remoteproc";
+ xlnx,cluster-mode = <1>;
+ ranges;
+ reg = <0x00 0xff9a0000 0x00 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ r5f_0 {
+ compatible = "xilinx,r5f";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ sram = <&tcm_0a &tcm_0b>;
+ memory-region = <&rproc &rpu0vdev0buffer &rpu0vdev0vring0 &rpu0vdev0vring1>;
+ power-domain = <&zynqmp_firmware 0x07>;
+ mboxes = <&ipi1_mailbox_pmu1 0>, <&ipi1_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+
+ zynqmp_ipi1 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <&gic>;
+ interrupts = <0 29 4>;
+ xlnx,ipi-id = <7>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ipi1_mailbox_pmu1: mailbox@ff990600 {
+ reg = <0xff990600 0x20 0xff990620 0x20 0xff9900c0 0x20 0xff9900e0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <1>;
+ };
+ };
+
+ retimer_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
+
+ cpu_opp_table {
+ opp00 {
+ opp-hz = <0x00 329166666>;
+ };
+
+ opp01 {
+ opp-hz = <0x00 438888888>;
+ };
+
+ opp02 {
+ opp-hz = <0x00 658333333>;
+ };
+
+ opp03 {
+ opp-hz = <0x00 1316666666>;
+ };
+ };
+
+/*
+ Orinoco Mini board has a switch SJA1105S which lacks MDIO support.
+ MDIO lines from PHY are connected directly to GPIO pins 50 and 51.
+ Thus we should use MDIO GPIO bitbanging in order to get MDIO working on Orinoco Mini board.
+*/
+ mdio_gpio: mdio {
+ compatible = "virtual,mdio-gpio";
+ gpios = <&gpio 50 0>, <&gpio 51 0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&cci {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gic {
+ num_cpus = <2>;
+ num_interrupts = <96>;
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+/*
+ ZynqMP SoC has number of MIO (Multiplexed IO) pins which may be re-assigned as required.
+ We should not trust default states on power up and make them explicit in line with
+ Nile and Orinoco Mini schematics.
+
+ Pins 8 and 44 are power pins.
+ Pins 50 and 51 are MDIO GPIO bitbang pins.
+ Pins 64 to 75 are connected to RGMII interface of SJA1105S switch. In SOM documentation
+ these pins default to GEM3 *AND* USB1 (which is of course wrong: only one device may be
+ defaulted to on power up). Hence we are explicitly switch these pins to GEM3 (ethernet3 group).
+*/
+&pinctrl0 {
+ status = "okay";
+ gpio_pins: gpio_pins {
+ mux {
+ groups = "gpio0_8_grp", "gpio0_44_grp",
+ "gpio0_50_grp", "gpio0_51_grp";
+ function = "gpio0";
+ };
+ conf {
+ groups = "gpio0_8_grp", "gpio0_44_grp",
+ "gpio0_50_grp", "gpio0_51_grp";
+ bias-pull-up;
+ io-standard = <IO_STANDARD_LVCMOS18>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ drive-strength = <DRIVE_STRENGTH_12MA>;
+ };
+ };
+ gem3_pins: gem3_pins {
+ mux {
+ groups = "ethernet3_0_grp";
+ function = "ethernet3";
+ };
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+ };
+};
+
+/*
+ GPIO pins 8 and 44 controlling power on the boards. It appears that boards are powered on by default.
+ But we would like to be explicit and hog these pins in high state to keep power going.
+*/
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_pins>;
+ gpio_hog1: pwr-good-som {
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "pwr-good-som";
+ };
+ gpio_hog2: p-en-orinico {
+ gpio-hog;
+ gpios = <44 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "p-en-orinoco";
+ };
+};
+
+/*
+ Orinoco Mini has Texas Instruments DP83867 as PHY interface. We need to set delays on it as it is in RGMII-ID mode.
+ Also straps connected to this PHY set it to internal test mode on power up making PHY unusable. We need to add
+ rxctrl-strap-quirk to reset PHY back to normal operation mode. It also should be noted that starps on
+ Orinoco Mini have a bug in hardware as four straps are grounded with 50 milliohm resistors and it does not align with PHY datasheet.
+*/
+&mdio_gpio {
+ phy0: ethernet-phy@0 {
+ reg = <0x3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+};
+
+/*
+ This is Cadence GEM interface. We should run it in RGMII mode with MAC only (signified by "fixed-link" setting).
+ As there no negotiation or MDIO we should fix it at 1 gigabit full-duplex. We also need to add empty MDIO as otherwise
+ this interface does not start.
+*/
+&gem3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gem3_pins>;
+ phy-connection-type = "rgmii";
+/* local-mac-address = [30 31 32 33 34 35]; */
+ nvmem = <&nvmem_firmware>;
+ oui = [DC 48 B2];
+ dna = <&efuse_dna>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+};
+
+/*
+ We should configure SPI bus as it is used to control SJA1105S switch.
+*/
+&spi0 {
+ status = "okay";
+ is-decoded-cs = <0>;
+ num-cs = <1>;
+ sja1105@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,sja1105s";
+ spi-max-frequency = <4000000>;
+ /* SPI settings to be used with SJA1105S based on its datasheet. spi-cpha is important as otherwise all data is shifted by one bit */
+ spi-cpha;
+ /* SJA1105S requires 500us delays. We will be generous and do 1000us */
+ fsl,spi-cs-sck-delay = <1000>;
+ fsl,spi-sck-cs-delay = <1000>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ /* External RJ45 connected to PHY on Orinoco Mini */
+ label = "eth0";
+ phy-handle = <&phy0>;
+ /* In role-mac phy-mode sets mode on PHY: we need it to be in RGMII-ID mode as port 0 is in MAC RGMII mode */
+ phy-mode = "rgmii-id";
+ reg = <0>;
+ /* Implicit "sja1105,role-mac;" */
+ };
+ port@1 {
+ /* Internal port connected to GEM3 */
+ ethernet = <&gem3>;
+ /* In role-phy phy-mode sets mode on switch port: we need it to be in RGMII-ID mode as GEM3 is in RGMII mode */
+ phy-mode = "rgmii-id";
+ reg = <1>;
+ /* Implicit "sja1105,role-phy;" */
+ /* We do not negotiate with GEM3 - just use fixed 1 gigabit full-duplex connection */
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&psgtr {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+ clock-frequency = <187500000>;
+ xlnx,mio-bank = <0>;
+ bus-width = <8>;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+ cts-override;
+ device_type = "serial";
+ port-number = <0>;
+};
+
+&watchdog0 {
+ status = "okay";
+ timeout-sec = <15>;
+};
+
+&lpd_watchdog {
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff -uNr linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
--- linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi 2025-03-25 02:39:08.000000000 +0000
+++ linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi 2025-03-28 00:20:30.000000000 +0000
@@ -133,7 +133,7 @@
};
&gpu {
- clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
+ clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
@@ -181,6 +181,7 @@
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem1 {
@@ -188,6 +189,7 @@
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem2 {
@@ -195,6 +197,7 @@
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem3 {
@@ -202,6 +205,7 @@
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+ assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gpio {
@@ -335,7 +339,3 @@
&zynqmp_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
-
-&zynqmp_pcap {
- clocks = <&zynqmp_clk PCAP>;
-};
diff -uNr linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/zynqmp.dtsi linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
--- linux-5.12.10-xilinx/arch/arm64/boot/dts/xilinx/zynqmp.dtsi 2025-03-25 02:39:08.000000000 +0000
+++ linux-5.12.10-nileorinocomini/arch/arm64/boot/dts/xilinx/zynqmp.dtsi 2025-03-28 00:20:30.000000000 +0000
@@ -33,6 +33,7 @@
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_cache>;
};
cpu1: cpu@1 {
@@ -42,6 +43,7 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_cache>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_cache>;
};
cpu3: cpu@3 {
@@ -60,6 +63,12 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_cache>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
idle-states {
@@ -101,7 +110,7 @@
};
};
- zynqmp_ipi: zynqmp_ipi {
+ zynqmp_ipi: zynqmp-ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
@@ -111,7 +120,7 @@
#size-cells = <2>;
ranges;
- ipi_mailbox_pmu1: mailbox@ff990400 {
+ ipi_mailbox_pmu1: mailbox@ff9905c0 {
u-boot,dm-pre-reloc;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
@@ -139,6 +148,10 @@
<0 144 4>,
<0 145 4>,
<0 146 4>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
};
psci {
@@ -149,9 +162,9 @@
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
- #power-domain-cells = <1>;
- method = "smc";
u-boot,dm-pre-reloc;
+ method = "smc";
+ #power-domain-cells = <1>;
zynqmp_power: zynqmp-power {
u-boot,dm-pre-reloc;
@@ -162,72 +175,67 @@
mbox-names = "tx", "rx";
};
- nvmem_firmware {
+ nvmem_firmware: nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
- soc_revision: soc_revision@0 {
+ soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
/* efuse access */
- efuse_dna: efuse_dna@c {
+ efuse_dna: efuse-dna@c {
reg = <0xc 0xc>;
};
- efuse_usr0: efuse_usr0@20 {
+ efuse_usr0: efuse-usr0@20 {
reg = <0x20 0x4>;
};
- efuse_usr1: efuse_usr1@24 {
+ efuse_usr1: efuse-usr1@24 {
reg = <0x24 0x4>;
};
- efuse_usr2: efuse_usr2@28 {
+ efuse_usr2: efuse-usr2@28 {
reg = <0x28 0x4>;
};
- efuse_usr3: efuse_usr3@2c {
+ efuse_usr3: efuse-usr3@2c {
reg = <0x2c 0x4>;
};
- efuse_usr4: efuse_usr4@30 {
+ efuse_usr4: efuse-usr4@30 {
reg = <0x30 0x4>;
};
- efuse_usr5: efuse_usr5@34 {
+ efuse_usr5: efuse-usr5@34 {
reg = <0x34 0x4>;
};
- efuse_usr6: efuse_usr6@38 {
+ efuse_usr6: efuse-usr6@38 {
reg = <0x38 0x4>;
};
- efuse_usr7: efuse_usr7@3c {
+ efuse_usr7: efuse-usr7@3c {
reg = <0x3c 0x4>;
};
- efuse_miscusr: efuse_miscusr@40 {
+ efuse_miscusr: efuse-miscusr@40 {
reg = <0x40 0x4>;
};
- efuse_chash: efuse_chash@50 {
+ efuse_chash: efuse-chash@50 {
reg = <0x50 0x4>;
};
- efuse_pufmisc: efuse_pufmisc@54 {
+ efuse_pufmisc: efuse-pufmisc@54 {
reg = <0x54 0x4>;
};
- efuse_sec: efuse_sec@58 {
+ efuse_sec: efuse-sec@58 {
reg = <0x58 0x4>;
};
- efuse_spkid: efuse_spkid@5c {
+ efuse_spkid: efuse-spkid@5c {
reg = <0x5c 0x4>;
};
- efuse_ppk0hash: efuse_ppk0hash@a0 {
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
reg = <0xa0 0x30>;
};
- efuse_ppk1hash: efuse_ppk1hash@d0 {
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
reg = <0xd0 0x30>;
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
- clock-names = "ref_clk";
- };
-
- xlnx_aes: zynqmp-aes {
- compatible = "xlnx,zynqmp-aes";
};
zynqmp_reset: reset-controller {
@@ -240,14 +248,6 @@
status = "disabled";
};
- xlnx_keccak_384: sha384 {
- compatible = "xlnx,zynqmp-keccak-384";
- };
-
- xlnx_rsa: zynqmp-rsa {
- compatible = "xlnx,zynqmp-rsa";
- };
-
modepin_gpio: gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
@@ -293,6 +293,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
@@ -305,6 +306,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
@@ -336,10 +338,10 @@
interrupt-parent = <&gic>;
interrupts = <0 124 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e8>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan2: dma-controller@fd510000 {
@@ -349,10 +351,10 @@
interrupt-parent = <&gic>;
interrupts = <0 125 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14e9>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan3: dma-controller@fd520000 {
@@ -362,10 +364,10 @@
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ea>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan4: dma-controller@fd530000 {
@@ -375,10 +377,10 @@
interrupt-parent = <&gic>;
interrupts = <0 127 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14eb>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan5: dma-controller@fd540000 {
@@ -388,10 +390,10 @@
interrupt-parent = <&gic>;
interrupts = <0 128 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ec>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan6: dma-controller@fd550000 {
@@ -401,10 +403,10 @@
interrupt-parent = <&gic>;
interrupts = <0 129 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ed>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan7: dma-controller@fd560000 {
@@ -414,10 +416,10 @@
interrupt-parent = <&gic>;
interrupts = <0 130 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ee>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
fpd_dma_chan8: dma-controller@fd570000 {
@@ -427,10 +429,10 @@
interrupt-parent = <&gic>;
interrupts = <0 131 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <128>;
iommus = <&smmu 0x14ef>;
power-domains = <&zynqmp_firmware PD_GDMA>;
- #dma-cells = <1>;
};
gic: interrupt-controller@f9010000 {
@@ -447,12 +449,12 @@
gpu: gpu@fd4b0000 {
status = "disabled";
- compatible = "arm,mali-400", "arm,mali-utgard";
+ compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
- interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
- clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
+ clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
@@ -467,10 +469,10 @@
interrupt-parent = <&gic>;
interrupts = <0 77 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan2: dma-controller@ffa90000 {
@@ -480,10 +482,10 @@
interrupt-parent = <&gic>;
interrupts = <0 78 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan3: dma-controller@ffaa0000 {
@@ -493,10 +495,10 @@
interrupt-parent = <&gic>;
interrupts = <0 79 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan4: dma-controller@ffab0000 {
@@ -506,10 +508,10 @@
interrupt-parent = <&gic>;
interrupts = <0 80 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan5: dma-controller@ffac0000 {
@@ -519,10 +521,10 @@
interrupt-parent = <&gic>;
interrupts = <0 81 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan6: dma-controller@ffad0000 {
@@ -532,10 +534,10 @@
interrupt-parent = <&gic>;
interrupts = <0 82 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan7: dma-controller@ffae0000 {
@@ -545,10 +547,10 @@
interrupt-parent = <&gic>;
interrupts = <0 83 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
lpd_dma_chan8: dma-controller@ffaf0000 {
@@ -558,10 +560,10 @@
interrupt-parent = <&gic>;
interrupts = <0 84 4>;
clock-names = "clk_main", "clk_apb";
+ #dma-cells = <1>;
xlnx,bus-width = <64>;
/* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
- #dma-cells = <1>;
};
mc: memory-controller@fd070000 {
@@ -585,7 +587,7 @@
};
gem0: ethernet@ff0b0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
@@ -596,10 +598,11 @@
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
+ reset-names = "gem0_rst";
};
gem1: ethernet@ff0c0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
@@ -610,10 +613,11 @@
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+ reset-names = "gem1_rst";
};
gem2: ethernet@ff0d0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
@@ -624,10 +628,11 @@
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
+ reset-names = "gem2_rst";
};
gem3: ethernet@ff0e0000 {
- compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem";
+ compatible = "xlnx,zynqmp-gem", "cdns,gem";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
@@ -638,6 +643,7 @@
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
+ reset-names = "gem3_rst";
};
gpio: gpio@ff0a0000 {
@@ -658,6 +664,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -669,6 +676,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
+ clock-frequency = <400000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -773,12 +781,12 @@
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
- bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ bus-range = <0x00 0xff>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
@@ -848,11 +856,10 @@
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- xlnx,device_id = <0>;
iommus = <&smmu 0x870>;
+ power-domains = <&zynqmp_firmware PD_SD_0>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
- power-domains = <&zynqmp_firmware PD_SD_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>;
};
@@ -864,15 +871,14 @@
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- xlnx,device_id = <1>;
iommus = <&smmu 0x871>;
+ power-domains = <&zynqmp_firmware PD_SD_1>;
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
- power-domains = <&zynqmp_firmware PD_SD_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>;
};
- smmu: iommu@fd800000 {
+ smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
#iommu-cells = <1>;
@@ -972,7 +978,7 @@
power-domains = <&zynqmp_firmware PD_UART_1>;
};
- usb0: usb0@ff9d0000 {
+ usb0: usb@ff9d0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
@@ -996,17 +1002,14 @@
interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
- snps,refclk_fladj;
clock-names = "ref";
- snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
- snps,xhci-reset-on-resume;
- snps,xhci-stream-quirk;
+ snps,resume-hs-terminations;
/* dma-coherent; */
};
};
- usb1: usb1@ff9e0000 {
+ usb1: usb@ff9e0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
@@ -1029,12 +1032,9 @@
interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
- snps,refclk_fladj;
clock-names = "ref";
- snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
- snps,xhci-reset-on-resume;
- snps,xhci-stream-quirk;
+ snps,resume-hs-terminations;
/* dma-coherent; */
};
};
@@ -1063,24 +1063,22 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
- interrupt-names = "ams-irq";
reg = <0x0 0xffa50000 0x0 0x800>;
- reg-names = "ams-base";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
#io-channel-cells = <1>;
- ranges;
+ ranges = <0 0 0xffa50800 0x800>;
- ams_ps: ams_ps@ffa50800 {
+ ams_ps: ams-ps@0 {
compatible = "xlnx,zynqmp-ams-ps";
status = "disabled";
- reg = <0x0 0xffa50800 0x0 0x400>;
+ reg = <0x0 0x400>;
};
- ams_pl: ams_pl@ffa50c00 {
+ ams_pl: ams-pl@400 {
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
- reg = <0x0 0xffa50c00 0x0 0x400>;
+ reg = <0x400 0x400>;
};
};
@@ -1097,7 +1095,7 @@
#dma-cells = <1>;
};
- zynqmp_dpaud_setting: dp_aud@fd4ac000 {
+ zynqmp_dpaud_setting: dp-aud@fd4ac000 {
compatible = "xlnx,zynqmp-dpaud-setting", "syscon";
reg = <0x0 0xfd4ac000 0x0 0x1000>;
};
@@ -1130,24 +1128,24 @@
i2c-bus {
};
- zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
+ zynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
};
- zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
+ zynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 {
compatible = "xlnx,dp-snd-pcm0";
dmas = <&zynqmp_dpdma 4>;
dma-names = "tx";
};
- zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
+ zynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 {
compatible = "xlnx,dp-snd-pcm1";
dmas = <&zynqmp_dpdma 5>;
dma-names = "tx";
};
- zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
+ zynqmp_dp_snd_card0: zynqmp-dp-snd-card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
<&zynqmp_dp_snd_pcm1>;
diff -uNr linux-5.12.10-xilinx/arch/arm64/configs/zynqmp_nileorinocomini_defconfig linux-5.12.10-nileorinocomini/arch/arm64/configs/zynqmp_nileorinocomini_defconfig
--- linux-5.12.10-xilinx/arch/arm64/configs/zynqmp_nileorinocomini_defconfig 1970-01-01 00:00:00.000000000 +0000
+++ linux-5.12.10-nileorinocomini/arch/arm64/configs/zynqmp_nileorinocomini_defconfig 2025-03-28 00:20:30.000000000 +0000
@@ -0,0 +1,248 @@
+# CONFIG_XEN is not set
+# CONFIG_ARM64_CRYPTO is not set
+# CONFIG_BT is not set
+CONFIG_SYSVIPC=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_NR_CPUS=8
+CONFIG_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_CMA=y
+CONFIG_CMA_SIZE_MBYTES=700
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE=y
+CONFIG_NET_PKTGEN=y
+CONFIG_CFG80211=m
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_CERTIFICATION_ONUS=y
+CONFIG_CFG80211_REG_CELLULAR_HINTS=y
+CONFIG_CFG80211_REG_RELAX_NO_IR=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_MAC80211_DEBUG_MENU=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_NET_9P=y
+CONFIG_PCI=y
+CONFIG_PCIE_XILINX_NWL=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_CONFIGFS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_XILINX_JESD204B=y
+CONFIG_XILINX_JESD204B_PHY=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_TI_ST=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_MACB=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_ZYNQMP_FIRMWARE_DEBUG=y
+CONFIG_ZYNQMP_FIRMWARE=y
+CONFIG_DP83867_PHY=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_CADENCE=y
+CONFIG_I2C_XILINX=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_PMBUS=y
+CONFIG_WATCHDOG=y
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_EDAC=y
+CONFIG_EDAC_SYNOPSYS=y
+CONFIG_EDAC_ZYNQMP_OCM=y
+CONFIG_DMATEST=y
+CONFIG_UIO_XILINX_APM=y
+CONFIG_STAGING=y
+CONFIG_XILINX_FCLK=y
+CONFIG_COMMON_CLK_SI5341=y
+CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
+CONFIG_IIO=y
+CONFIG_XILINX_INTC=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_ARM_CCI_PMU=y
+CONFIG_NVMEM_ZYNQMP=y
+CONFIG_FPGA=y
+CONFIG_FPGA_REGION=y
+CONFIG_OF_FPGA_REGION=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_BTRFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFSD=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_DMA_CMA=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_XILINX_AXI_EMAC=y
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_XILINX=y
+CONFIG_COMMON_CLK_ZYNQMP=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_EDAC_XILINX_DDR=y
+CONFIG_EDAC_DEBUG=y
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_UIO_XILINX_AI_ENGINE=y
+CONFIG_SRAM=y
+CONFIG_I2C_MUX_PCA9541=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_REGULATOR_DA9062=y
+# CONFIG_DA9062_WATCHDOG is not set
+CONFIG_NVME_CORE=y
+CONFIG_IPV6=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_64BIT=y
+CONFIG_MMU=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_KEXEC=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCIE_XDMA_PL=y
+CONFIG_XILINX_PS_PCIE_DMA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_SNMP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_DP83848_PHY=y
+CONFIG_GENERIC_PHY=y
+CONFIG_XILINX_APF=y
+CONFIG_XILINX_DMA_APF=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_ZONE_DEVICE=y
+CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_MIGRATION=y
+CONFIG_XILINX_TRAFGEN=y
+CONFIG_XILINX_AIE=y
+CONFIG_MFD_DA9063=y
+CONFIG_RTC_DRV_DA9063=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_XILINX_ZYNQMP_DMA=y
+# CONFIG_XILINX_DMA is not set
+CONFIG_FPGA_BRIDGE=y
+CONFIG_SMP=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
diff -uNr linux-5.12.10-xilinx/drivers/gpu/drm/drm_atomic_helper.c linux-5.12.10-nileorinocomini/drivers/gpu/drm/drm_atomic_helper.c
--- linux-5.12.10-xilinx/drivers/gpu/drm/drm_atomic_helper.c 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/drivers/gpu/drm/drm_atomic_helper.c 2025-03-28 00:20:30.000000000 +0000
@@ -1509,8 +1509,8 @@
drm_crtc_vblank_count(crtc),
msecs_to_jiffies(100));
- WARN(!ret, "[CRTC:%d:%s] vblank wait timed out\n",
- crtc->base.id, crtc->name);
+// WARN(!ret, "[CRTC:%d:%s] vblank wait timed out\n",
+// crtc->base.id, crtc->name);
drm_crtc_vblank_put(crtc);
}
diff -uNr linux-5.12.10-xilinx/drivers/infiniband/core/device.c linux-5.12.10-nileorinocomini/drivers/infiniband/core/device.c
--- linux-5.12.10-xilinx/drivers/infiniband/core/device.c 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/drivers/infiniband/core/device.c 2025-03-28 00:20:30.000000000 +0000
@@ -2695,6 +2695,7 @@
SET_DEVICE_OP(dev_ops, read_counters);
SET_DEVICE_OP(dev_ops, reg_dm_mr);
SET_DEVICE_OP(dev_ops, reg_user_mr);
+ SET_DEVICE_OP(dev_ops, reg_user_mr_ex);
SET_DEVICE_OP(dev_ops, reg_user_mr_dmabuf);
SET_DEVICE_OP(dev_ops, req_ncomp_notif);
SET_DEVICE_OP(dev_ops, req_notify_cq);
diff -uNr linux-5.12.10-xilinx/drivers/infiniband/core/rdma_core.c linux-5.12.10-nileorinocomini/drivers/infiniband/core/rdma_core.c
--- linux-5.12.10-xilinx/drivers/infiniband/core/rdma_core.c 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/drivers/infiniband/core/rdma_core.c 2025-03-28 00:20:30.000000000 +0000
@@ -899,7 +899,9 @@
* if we hit this WARN_ON, that means we are
* racing with a lookup_get.
*/
+#if 0
WARN_ON(uverbs_try_lock_object(obj, UVERBS_LOOKUP_WRITE));
+#endif
if (reason == RDMA_REMOVE_DRIVER_FAILURE)
obj->object = NULL;
if (!uverbs_destroy_uobject(obj, reason, &attrs))
diff -uNr linux-5.12.10-xilinx/drivers/infiniband/core/uverbs_cmd.c linux-5.12.10-nileorinocomini/drivers/infiniband/core/uverbs_cmd.c
--- linux-5.12.10-xilinx/drivers/infiniband/core/uverbs_cmd.c 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/drivers/infiniband/core/uverbs_cmd.c 2025-03-28 00:20:30.000000000 +0000
@@ -692,6 +692,83 @@
return 0;
}
+static int ib_uverbs_reg_mr_ex(struct uverbs_attr_bundle *attrs)
+{
+ struct ib_uverbs_reg_mr_resp resp = {};
+ struct ib_uverbs_reg_mr cmd;
+ struct ib_uobject *uobj;
+ struct ib_pd *pd;
+ struct ib_mr *mr;
+ int ret;
+ struct ib_device *ib_dev;
+
+ ret = uverbs_request(attrs, &cmd, sizeof(cmd));
+ if (ret)
+ return ret;
+
+ if ((cmd.start & ~PAGE_MASK) != (cmd.hca_va & ~PAGE_MASK))
+ return -EINVAL;
+
+ ret = ib_check_mr_access(ib_dev, cmd.access_flags);
+ if (ret)
+ return ret;
+
+ uobj = uobj_alloc(UVERBS_OBJECT_MR, attrs, &ib_dev);
+ if (IS_ERR(uobj))
+ return PTR_ERR(uobj);
+
+ pd = uobj_get_obj_read(pd, UVERBS_OBJECT_PD, cmd.pd_handle, attrs);
+ if (!pd) {
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ if (cmd.access_flags & IB_ACCESS_ON_DEMAND) {
+ if (!(pd->device->attrs.device_cap_flags &
+ IB_DEVICE_ON_DEMAND_PAGING)) {
+ pr_debug("ODP support not available\n");
+ ret = -EINVAL;
+ goto err_put;
+ }
+ }
+
+ mr = pd->device->ops.reg_user_mr_ex(pd, cmd.start, cmd.length, cmd.hca_va,
+ cmd.access_flags,
+ &attrs->driver_udata);
+ if (IS_ERR(mr)) {
+ ret = PTR_ERR(mr);
+ goto err_put;
+ }
+
+ mr->device = pd->device;
+ mr->pd = pd;
+ mr->type = IB_MR_TYPE_USER;
+ mr->dm = NULL;
+ mr->sig_attrs = NULL;
+ mr->uobject = uobj;
+ atomic_inc(&pd->usecnt);
+ mr->iova = cmd.hca_va;
+
+ rdma_restrack_new(&mr->res, RDMA_RESTRACK_MR);
+ rdma_restrack_set_name(&mr->res, NULL);
+ rdma_restrack_add(&mr->res);
+
+ uobj->object = mr;
+ uobj_put_obj_read(pd);
+ uobj_finalize_uobj_create(uobj, attrs);
+
+ resp.lkey = mr->lkey;
+ resp.rkey = mr->rkey;
+ resp.mr_handle = uobj->id;
+ return uverbs_response(attrs, &resp, sizeof(resp));
+
+err_put:
+ uobj_put_obj_read(pd);
+err_free:
+ uobj_alloc_abort(uobj, attrs);
+ return ret;
+}
+
static int ib_uverbs_reg_mr(struct uverbs_attr_bundle *attrs)
{
struct ib_uverbs_reg_mr_resp resp = {};
@@ -3847,6 +3924,12 @@
struct ib_uverbs_reg_mr_resp),
UAPI_DEF_METHOD_NEEDS_FN(reg_user_mr)),
DECLARE_UVERBS_WRITE(
+ IB_USER_VERBS_CMD_REG_MR_EX,
+ ib_uverbs_reg_mr_ex,
+ UAPI_DEF_WRITE_UDATA_IO(struct ib_uverbs_reg_mr,
+ struct ib_uverbs_reg_mr_resp),
+ UAPI_DEF_METHOD_NEEDS_FN(reg_user_mr_ex)),
+ DECLARE_UVERBS_WRITE(
IB_USER_VERBS_CMD_REREG_MR,
ib_uverbs_rereg_mr,
UAPI_DEF_WRITE_UDATA_IO(struct ib_uverbs_rereg_mr,
diff -uNr linux-5.12.10-xilinx/drivers/net/ethernet/cadence/macb_main.c linux-5.12.10-nileorinocomini/drivers/net/ethernet/cadence/macb_main.c
--- linux-5.12.10-xilinx/drivers/net/ethernet/cadence/macb_main.c 2025-03-25 03:42:36.000000000 +0000
+++ linux-5.12.10-nileorinocomini/drivers/net/ethernet/cadence/macb_main.c 2025-03-28 00:15:08.000000000 +0000
@@ -38,8 +38,12 @@
#include <linux/crc32.h>
#include <linux/inetdevice.h>
#include <linux/reset.h>
+#include <linux/nvmem-consumer.h>
#include "macb.h"
+/* Length of Organization Unique Identifier */
+#define OUI_LEN 3
+
/* This structure is only used for MACB on SiFive FU540 devices */
struct sifive_fu540_macb_mgmt {
void __iomem *reg;
@@ -4685,6 +4689,16 @@
struct macb *bp;
int err, val;
+ struct nvmem_device *nvmem;
+ struct device_node *efuse_dna_node;
+ int len;
+ const u8 *oui;
+ u32 dna_pos[2];
+ u8 dna[12];
+ u8 addr[ETH_ALEN];
+ bool dna_set;
+ int ret;
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mem = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(mem))
@@ -4727,6 +4741,7 @@
err = -ENOMEM;
goto err_disable_clocks;
}
+ strcpy(dev->name, "gem%d");
dev->base_addr = regs->start;
@@ -4805,7 +4820,37 @@
} else if (!IS_ERR_OR_NULL(mac)) {
ether_addr_copy(bp->dev->dev_addr, mac);
} else {
- macb_get_hwaddr(bp);
+ dna_set = false;
+ oui = of_get_property(np, "oui", &len);
+ if (oui && len == OUI_LEN) {
+ nvmem = of_nvmem_device_get(np, NULL);
+ if (!IS_ERR(nvmem)) {
+ efuse_dna_node = of_parse_phandle(np, "dna", 0);
+ if (efuse_dna_node) {
+ ret = of_property_read_u32_array(efuse_dna_node, "reg", dna_pos, 2);
+ if (ret == 0) {
+ ret = nvmem_device_read(nvmem, dna_pos[0], dna_pos[1], dna);
+ if (ret >= 0) {
+ addr[0] = oui[0];
+ addr[1] = oui[1];
+ addr[2] = oui[2];
+ addr[3] = dna[0];
+ addr[4] = dna[1];
+ addr[5] = dna[2];
+ if (is_valid_ether_addr(addr)) {
+ memcpy(bp->dev->dev_addr, addr, sizeof(addr));
+ dna_set = true;
+ }
+ }
+ }
+ of_node_put(efuse_dna_node);
+ }
+ nvmem_device_put(nvmem);
+ }
+ }
+ if (!dna_set) {
+ macb_get_hwaddr(bp);
+ }
}
err = of_get_phy_mode(np, &interface);
diff -uNr linux-5.12.10-xilinx/include/rdma/ib_verbs.h linux-5.12.10-nileorinocomini/include/rdma/ib_verbs.h
--- linux-5.12.10-xilinx/include/rdma/ib_verbs.h 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/include/rdma/ib_verbs.h 2025-03-28 00:20:30.000000000 +0000
@@ -43,6 +43,8 @@
#include <uapi/rdma/rdma_user_ioctl.h>
#include <uapi/rdma/ib_user_ioctl_verbs.h>
+#define IB_CHANGES_XIB_NVMF
+
#define IB_FW_VERSION_NAME_MAX ETHTOOL_FWVERS_LEN
struct ib_umem_odp;
@@ -1237,6 +1239,11 @@
IB_QP_RATE_LIMIT = (1<<25),
IB_QP_ATTR_STANDARD_BITS = GENMASK(20, 0),
+#ifdef IB_CHANGES_XIB_NVMF
+ IB_QP_RST_RQ = (1<<26),
+ IB_QP_RST_SQ_CQ = (1<<27),
+ IB_ENABLE_QP_HW_ACCL = (1<<28),
+#endif
};
enum ib_qp_state {
@@ -1288,6 +1295,15 @@
u8 alt_timeout;
u32 rate_limit;
struct net_device *xmit_slave;
+#ifdef IB_CHANGES_XIB_NVMF
+ union {
+ int nvmf_rhost;
+ /* Rx packets to be processed */
+ int rx_pkt_pending;
+ };
+ dma_addr_t rq_ba_p;
+ dma_addr_t sq_ba_p;
+#endif
};
enum ib_wr_opcode {
@@ -2434,6 +2450,9 @@
struct ib_mr *(*reg_user_mr)(struct ib_pd *pd, u64 start, u64 length,
u64 virt_addr, int mr_access_flags,
struct ib_udata *udata);
+ struct ib_mr *(*reg_user_mr_ex)(struct ib_pd *pd, u64 start, u64 length,
+ u64 virt_addr, int mr_access_flags,
+ struct ib_udata *udata);
struct ib_mr *(*reg_user_mr_dmabuf)(struct ib_pd *pd, u64 offset,
u64 length, u64 virt_addr, int fd,
int mr_access_flags,
diff -uNr linux-5.12.10-xilinx/include/uapi/rdma/ib_user_ioctl_verbs.h linux-5.12.10-nileorinocomini/include/uapi/rdma/ib_user_ioctl_verbs.h
--- linux-5.12.10-xilinx/include/uapi/rdma/ib_user_ioctl_verbs.h 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/include/uapi/rdma/ib_user_ioctl_verbs.h 2025-03-28 00:20:30.000000000 +0000
@@ -249,6 +249,7 @@
RDMA_DRIVER_QIB,
RDMA_DRIVER_EFA,
RDMA_DRIVER_SIW,
+ RDMA_DRIVER_XLNX,
};
enum ib_uverbs_gid_type {
diff -uNr linux-5.12.10-xilinx/include/uapi/rdma/ib_user_verbs.h linux-5.12.10-nileorinocomini/include/uapi/rdma/ib_user_verbs.h
--- linux-5.12.10-xilinx/include/uapi/rdma/ib_user_verbs.h 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/include/uapi/rdma/ib_user_verbs.h 2025-03-28 00:20:30.000000000 +0000
@@ -87,6 +87,7 @@
IB_USER_VERBS_CMD_OPEN_XRCD,
IB_USER_VERBS_CMD_CLOSE_XRCD,
IB_USER_VERBS_CMD_CREATE_XSRQ,
+ IB_USER_VERBS_CMD_REG_MR_EX,
IB_USER_VERBS_CMD_OPEN_QP,
};
diff -uNr linux-5.12.10-xilinx/include/uapi/rdma/xib-abi.h linux-5.12.10-nileorinocomini/include/uapi/rdma/xib-abi.h
--- linux-5.12.10-xilinx/include/uapi/rdma/xib-abi.h 1970-01-01 00:00:00.000000000 +0000
+++ linux-5.12.10-nileorinocomini/include/uapi/rdma/xib-abi.h 2025-03-28 00:20:30.000000000 +0000
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018 Xilinx Inc.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef XIB_ABI_USER_H
+#define XIB_ABI_USER_H
+
+#include <linux/types.h>
+
+struct xib_ib_create_cq {
+ __aligned_u64 buf_addr;
+ __aligned_u64 db_addr;
+};
+
+struct xib_ib_create_qp {
+ __aligned_u64 db_addr;
+ __aligned_u64 sq_ba;
+ __aligned_u64 rq_ba;
+ __aligned_u64 cq_ba;
+ __aligned_u64 imm_inv_ba;
+};
+
+struct xib_ib_alloc_pd_resp {
+ __u32 pdn;
+};
+
+struct xib_ib_create_cq_resp {
+ __aligned_u64 cqn;
+ __aligned_u64 cap_flags;
+};
+
+struct xib_ib_create_qp_resp {
+ __u32 qpn;
+ __u32 cap_flags;
+};
+
+struct xib_ib_alloc_ucontext_resp {
+ __aligned_u64 db_pa;
+ __u32 db_size;
+ __aligned_u64 cq_ci_db_pa;
+ __aligned_u64 rq_pi_db_pa;
+ uint32_t cq_ci_db_size, rq_pi_db_size;
+ __u32 qp_tab_size;
+};
+
+#endif /* XIB_ABI_USER_H */
diff -uNr linux-5.12.10-xilinx/mm/Kconfig linux-5.12.10-nileorinocomini/mm/Kconfig
--- linux-5.12.10-xilinx/mm/Kconfig 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/mm/Kconfig 2025-03-28 00:20:30.000000000 +0000
@@ -280,6 +280,9 @@
config PHYS_ADDR_T_64BIT
def_bool 64BIT
+config ARCH_MEMORY_PROBE
+ def_bool y
+ depends on MEMORY_HOTPLUG
config BOUNCE
bool "Enable bounce buffers"
default y
diff -uNr linux-5.12.10-xilinx/sound/soc/soc-dai.c linux-5.12.10-nileorinocomini/sound/soc/soc-dai.c
--- linux-5.12.10-xilinx/sound/soc/soc-dai.c 2021-06-10 11:41:49.000000000 +0000
+++ linux-5.12.10-nileorinocomini/sound/soc/soc-dai.c 2025-03-28 00:20:30.000000000 +0000
@@ -24,9 +24,12 @@
case -ENOTSUPP:
break;
default:
+#if 0
dev_err(dai->dev,
"ASoC: error at %s on %s: %d\n",
func, dai->name, ret);
+#endif
+ break;
}
return ret;
diff -uNr linux-5.12.10-xilinx/sound/soc/xilinx/xlnx_formatter_pcm.c linux-5.12.10-nileorinocomini/sound/soc/xilinx/xlnx_formatter_pcm.c
--- linux-5.12.10-xilinx/sound/soc/xilinx/xlnx_formatter_pcm.c 2025-03-25 02:39:08.000000000 +0000
+++ linux-5.12.10-nileorinocomini/sound/soc/xilinx/xlnx_formatter_pcm.c 2025-03-28 00:20:30.000000000 +0000
@@ -379,11 +379,12 @@
stream_data->xfer_mode = (val & data_xfer_mode) >> data_xfer_shift;
stream_data->ch_limit = (val & ch_count_mask) >> ch_count_shift;
+#if 0
dev_info(component->dev,
"stream %d : format = %d mode = %d ch_limit = %d\n",
substream->stream, stream_data->interleaved,
stream_data->xfer_mode, stream_data->ch_limit);
-
+#endif
snd_soc_set_runtime_hwparams(substream, &xlnx_pcm_hardware);
runtime->private_data = stream_data;
linux-5.12.10-xilinx.patch
View file @ fca85a9a
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