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Commit 918df1a6 authored by Vladimir Bashkirtsev's avatar Vladimir Bashkirtsev
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Added watchdog for Odroid HC2

parent a88fb099
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Makefile
View file @ 918df1a6
...@@ -195,6 +195,7 @@ export FW_ENV_OPIPCPLUS_MENDER ...@@ -195,6 +195,7 @@ export FW_ENV_OPIPCPLUS_MENDER
odroidhc2: odroidhc2-boot-cmd odroidhc2-fw_env.config odroidhc2: odroidhc2-boot-cmd odroidhc2-fw_env.config
tar xf u-boot-2020.04.tar.bz2 tar xf u-boot-2020.04.tar.bz2
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-odroid_board_detection_fix.patch
$(MAKE) -C u-boot-2020.04 odroid-xu3_defconfig $(MAKE) -C u-boot-2020.04 odroid-xu3_defconfig
@echo "# CONFIG_ENV_IS_IN_FAT is not set" >> u-boot-2020.04/.config @echo "# CONFIG_ENV_IS_IN_FAT is not set" >> u-boot-2020.04/.config
@echo "CONFIG_ENV_IS_IN_MMC=y" >> u-boot-2020.04/.config @echo "CONFIG_ENV_IS_IN_MMC=y" >> u-boot-2020.04/.config
...@@ -241,6 +242,8 @@ odroidhc2-mender: odroidhc2-boot-cmd-mender odroidhc2-fw_env.config-mender ...@@ -241,6 +242,8 @@ odroidhc2-mender: odroidhc2-boot-cmd-mender odroidhc2-fw_env.config-mender
tar xf u-boot-2020.04.tar.bz2 tar xf u-boot-2020.04.tar.bz2
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-mender.patch patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-mender.patch
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-odroid_board_detection_fix.patch
patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-exynos_wdt.patch
$(MAKE) -C u-boot-2020.04 odroid-xu3_defconfig $(MAKE) -C u-boot-2020.04 odroid-xu3_defconfig
@echo "# CONFIG_ENV_IS_NOWHERE is not set" >> u-boot-2020.04/.config @echo "# CONFIG_ENV_IS_NOWHERE is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_ENV_IS_IN_FAT is not set" >> u-boot-2020.04/.config @echo "# CONFIG_ENV_IS_IN_FAT is not set" >> u-boot-2020.04/.config
...@@ -248,6 +251,16 @@ odroidhc2-mender: odroidhc2-boot-cmd-mender odroidhc2-fw_env.config-mender ...@@ -248,6 +251,16 @@ odroidhc2-mender: odroidhc2-boot-cmd-mender odroidhc2-fw_env.config-mender
@echo "CONFIG_SYS_REDUNDAND_ENVIRONMENT=y" >> u-boot-2020.04/.config @echo "CONFIG_SYS_REDUNDAND_ENVIRONMENT=y" >> u-boot-2020.04/.config
@echo "# CONFIG_ENV_OFFSET is not set" >> u-boot-2020.04/.config @echo "# CONFIG_ENV_OFFSET is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_ENV_OFFSET_REDUND is not set" >> u-boot-2020.04/.config @echo "# CONFIG_ENV_OFFSET_REDUND is not set" >> u-boot-2020.04/.config
@echo "CONFIG_WDT=y" >> u-boot-2020.04/.config
@echo "# CONFIG_CMD_WDT is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_WDT_AT91 is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_WDT_CDNS is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_WDT_CORTINA is not set" >> u-boot-2020.04/.config
@echo "CONFIG_WDT_EXYNOS=y" >> u-boot-2020.04/.config
@echo "# CONFIG_WDT_SP805 is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_WDT_STM32MP is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_XILINX_TB_WATCHDOG is not set" >> u-boot-2020.04/.config
@echo "# CONFIG_HBMC_AM654 is not set" >> u-boot-2020.04/.config
$(MAKE) -C u-boot-2020.04 oldconfig $(MAKE) -C u-boot-2020.04 oldconfig
$(MAKE) -C u-boot-2020.04 $(MAKE) -C u-boot-2020.04
mount /dev/$(DISK)1 /uboot mount /dev/$(DISK)1 /uboot
......
u-boot-2020.04-exynos_wdt.patch 0 → 100644
View file @ 918df1a6
diff -uNr u-boot-2020.04/arch/arm/dts/exynos5250.dtsi u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos5250.dtsi
--- u-boot-2020.04/arch/arm/dts/exynos5250.dtsi 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos5250.dtsi 2022-01-02 06:03:27.582648707 +0000
@@ -120,6 +120,17 @@
};
};
+ watchdog@101d0000 {
+ compatible = "samsung,exynos5250-wdt";
+ reg = <0x101D0000 0x100>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
+
+ pmu_system_controller: system-controller@10040000 {
+ compatible = "samsung,exynos5250-pmu", "syscon";
+ reg = <0x10040000 0x5000>;
+ };
+
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
diff -uNr u-boot-2020.04/arch/arm/dts/exynos54xx.dtsi u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos54xx.dtsi
--- u-boot-2020.04/arch/arm/dts/exynos54xx.dtsi 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos54xx.dtsi 2022-01-02 03:55:22.324186023 +0000
@@ -210,6 +210,17 @@
mem-type = "ddr3";
};
+ wdt: watchdog@101d0000 {
+ compatible = "samsung,exynos5420-wdt";
+ reg = <0x101d0000 0x100>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
+
+ pmu_system_controller: system-controller@10040000 {
+ compatible = "samsung,exynos5420-pmu", "syscon";
+ reg = <0x10040000 0x5000>;
+ };
+
pwm: pwm@12dd0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x12dd0000 0x100>;
diff -uNr u-boot-2020.04/arch/arm/dts/exynos7420.dtsi u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos7420.dtsi
--- u-boot-2020.04/arch/arm/dts/exynos7420.dtsi 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/arch/arm/dts/exynos7420.dtsi 2022-01-02 06:09:27.195643087 +0000
@@ -79,4 +79,15 @@
pinctrl-names = "default";
pinctrl-0 = <&serial2_bus>;
};
+
+ watchdog: watchdog@101d0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x101d0000 0x100>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ };
+
+ pmu_system_controller: system-controller@10040000 {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x105c0000 0x5000>;
+ };
};
diff -uNr u-boot-2020.04/board/samsung/common/board.c u-boot-2020.04-exynos_wdt/board/samsung/common/board.c
--- u-boot-2020.04/board/samsung/common/board.c 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/board/samsung/common/board.c 2022-01-02 06:12:20.839955900 +0000
@@ -32,6 +32,8 @@
#include <samsung/misc.h>
#include <dm/pinctrl.h>
#include <dm.h>
+#include <dm/uclass.h>
+#include <wdt.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -113,6 +115,20 @@
return exynos_init();
}
+#if defined CONFIG_WDT_EXYNOS
+static struct udevice *watchdog_dev = NULL;
+
+void arch_preboot_os(void)
+{
+ if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+ puts("Cannot find Exynos watchdog!\n");
+ } else {
+ wdt_start(watchdog_dev, (u64) 15 * 1000, 0);
+ puts("Watchdog engaged\n");
+ }
+}
+#endif
+
int dram_init(void)
{
unsigned int i;
diff -uNr u-boot-2020.04/drivers/watchdog/exynos_wdt.c u-boot-2020.04-exynos_wdt/drivers/watchdog/exynos_wdt.c
--- u-boot-2020.04/drivers/watchdog/exynos_wdt.c 1970-01-01 00:00:00.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/drivers/watchdog/exynos_wdt.c 2022-01-02 05:32:27.856245283 +0000
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * Copyright (c) 2021 Vladimir Bashkirtsev
+ *
+ * Exynos Watchdog Timer Support
+ *
+ * Based on, softdog.c by Alan Cox,
+ * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define EXYNOS_WTCON 0x00
+#define EXYNOS_WTDAT 0x04
+#define EXYNOS_WTCNT 0x08
+
+#define EXYNOS_WTCON_RSTEN (1 << 0)
+#define EXYNOS_WTCON_INTEN (1 << 2)
+#define EXYNOS_WTCON_ENABLE (1 << 5)
+
+#define EXYNOS_WTCON_DIV16 (0 << 3)
+#define EXYNOS_WTCON_DIV32 (1 << 3)
+#define EXYNOS_WTCON_DIV64 (2 << 3)
+#define EXYNOS_WTCON_DIV128 (3 << 3)
+
+#define EXYNOS_WTCON_PRESCALE(x) ((x) << 8)
+#define EXYNOS_WTCON_PRESCALE_MASK (0xff << 8)
+
+#define EXYNOS_WATCHDOG_DEFAULT_TIME (15)
+#define EXYNOS_WATCHDOG_CLOCK_FREQ 100000000
+
+#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
+#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
+
+/**
+ * struct exynos_wdt_variant - Per-variant config data
+ *
+ * @disable_reg: Offset in pmureg for the register that disables the watchdog
+ * timer reset functionality.
+ * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
+ * timer reset functionality.
+ * @mask_bit: Bit number for the watchdog timer in the disable register and the
+ * mask reset register.
+ */
+
+struct exynos_wdt_variant {
+ int disable_reg;
+ int mask_reset_reg;
+ int mask_bit;
+};
+
+struct exynos_wdt_priv {
+ unsigned int timeout;
+ unsigned int count;
+ void __iomem *wdt_base;
+ const struct exynos_wdt_variant *variant;
+ struct regmap *pmureg;
+};
+
+static int exynos_wdt_mask_and_disable_reset(struct exynos_wdt_priv *wdt, bool mask)
+{
+ int ret;
+ u32 mask_val = 1 << wdt->variant->mask_bit;
+ u32 val = 0;
+
+ if (mask)
+ val = mask_val;
+
+ ret = regmap_update_bits(wdt->pmureg,
+ wdt->variant->disable_reg,
+ mask_val, val);
+ if (ret < 0)
+ goto error;
+
+ ret = regmap_update_bits(wdt->pmureg,
+ wdt->variant->mask_reset_reg,
+ mask_val, val);
+ error:
+ if (ret < 0)
+ pr_err("failed to update reg(%d)\n", ret);
+
+ return ret;
+}
+
+static int exynos_wdt_set_heartbeat(struct udevice *dev, unsigned int timeout)
+{
+ struct exynos_wdt_priv *wdt = dev_get_priv(dev);
+ unsigned long freq = EXYNOS_WATCHDOG_CLOCK_FREQ;
+ unsigned int count;
+ unsigned int divisor = 1;
+ unsigned long wtcon;
+
+ if (timeout < 1)
+ return -EINVAL;
+
+ freq = DIV_ROUND_UP(freq, 128);
+ count = timeout * freq;
+
+ debug("Heartbeat: count=%d, timeout=%d, freq=%lu\n", count, timeout, freq);
+
+ /* if the count is bigger than the watchdog register,
+ then work out what we need to do (and if) we can
+ actually make this value
+ */
+
+ if (count >= 0x10000) {
+ divisor = DIV_ROUND_UP(count, 0xffff);
+
+ if (divisor > 0x100) {
+ debug("timeout %d too big\n", timeout);
+ return -EINVAL;
+ }
+ }
+
+ debug("Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
+ timeout, divisor, count, DIV_ROUND_UP(count, divisor));
+
+ count = DIV_ROUND_UP(count, divisor);
+ wdt->count = count;
+
+ /* update the pre-scaler */
+ wtcon = readl(wdt->wdt_base + EXYNOS_WTCON);
+ wtcon &= ~EXYNOS_WTCON_PRESCALE_MASK;
+ wtcon |= EXYNOS_WTCON_PRESCALE(divisor-1);
+
+ writel(count, wdt->wdt_base + EXYNOS_WTDAT);
+ writel(wtcon, wdt->wdt_base + EXYNOS_WTCON);
+
+ wdt->timeout = (count * divisor) / freq;
+
+ return 0;
+}
+
+static int exynos_wdt_ping(struct udevice *dev)
+{
+ struct exynos_wdt_priv *exynos_wdt = dev_get_priv(dev);
+ void __iomem *wdt_base = exynos_wdt->wdt_base;
+
+ writel(exynos_wdt->count, wdt_base + EXYNOS_WTCNT);
+
+ return 0;
+}
+
+static void __exynos_wdt_stop(struct exynos_wdt_priv *wdt)
+{
+ unsigned long wtcon;
+
+ wtcon = readl(wdt->wdt_base + EXYNOS_WTCON);
+ wtcon &= ~(EXYNOS_WTCON_ENABLE | EXYNOS_WTCON_RSTEN);
+ writel(wtcon, wdt->wdt_base + EXYNOS_WTCON);
+}
+
+static int exynos_wdt_stop(struct udevice *dev)
+{
+ struct exynos_wdt_priv *wdt = dev_get_priv(dev);
+
+ __exynos_wdt_stop(wdt);
+
+ return 0;
+}
+
+static int exynos_wdt_restart(struct udevice *dev, ulong flags)
+{
+ struct exynos_wdt_priv *exynos_wdt_priv = dev_get_priv(dev);
+ void __iomem *wdt_base = exynos_wdt_priv->wdt_base;
+
+ /* disable watchdog, to be safe */
+ writel(0, wdt_base + EXYNOS_WTCON);
+
+ /* put initial values into count and data */
+ writel(0x80, wdt_base + EXYNOS_WTCNT);
+ writel(0x80, wdt_base + EXYNOS_WTDAT);
+
+ /* set the watchdog to go and reset... */
+ writel(EXYNOS_WTCON_ENABLE | EXYNOS_WTCON_DIV16 |
+ EXYNOS_WTCON_RSTEN | EXYNOS_WTCON_PRESCALE(0x20),
+ wdt_base + EXYNOS_WTCON);
+
+ /* wait for reset to assert... */
+ mdelay(500);
+
+ return 0;
+}
+
+static int exynos_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ unsigned long wtcon;
+ struct exynos_wdt_priv *wdt = dev_get_priv(dev);
+
+ __exynos_wdt_stop(wdt);
+
+ wdt->timeout = timeout_ms / 1000;
+ exynos_wdt_set_heartbeat(dev, wdt->timeout);
+
+ wtcon = readl(wdt->wdt_base + EXYNOS_WTCON);
+ wtcon |= EXYNOS_WTCON_ENABLE | EXYNOS_WTCON_DIV128;
+
+ wtcon &= ~EXYNOS_WTCON_INTEN;
+ wtcon |= EXYNOS_WTCON_RSTEN;
+
+ debug("Starting watchdog: count=0x%08x, wtcon=%08lx\n",
+ wdt->count, wtcon);
+
+ writel(wdt->count, wdt->wdt_base + EXYNOS_WTDAT);
+ writel(wdt->count, wdt->wdt_base + EXYNOS_WTCNT);
+ writel(wtcon, wdt->wdt_base + EXYNOS_WTCON);
+
+ wtcon = readl(wdt->wdt_base + EXYNOS_WTCON);
+
+ debug("Watchdog %sactive, reset %sabled, irq %sabled\n",
+ (wtcon & EXYNOS_WTCON_ENABLE) ? "" : "in",
+ (wtcon & EXYNOS_WTCON_RSTEN) ? "en" : "dis",
+ (wtcon & EXYNOS_WTCON_INTEN) ? "en" : "dis");
+
+ return 0;
+}
+
+static const struct wdt_ops exynos_wdt_ops = {
+ .start = exynos_wdt_start,
+ .stop = exynos_wdt_stop,
+ .reset = exynos_wdt_ping,
+ .expire_now = exynos_wdt_restart,
+};
+
+static const struct exynos_wdt_variant drv_data_exynos5250 = {
+ .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 20,
+};
+
+static const struct exynos_wdt_variant drv_data_exynos5420 = {
+ .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 0,
+};
+
+static const struct exynos_wdt_variant drv_data_exynos7 = {
+ .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 23,
+};
+
+static const struct udevice_id exynos_wdt_ids[] = {
+ { .compatible = "samsung,exynos5250-wdt", .data = (ulong)&drv_data_exynos5250 },
+ { .compatible = "samsung,exynos5420-wdt", .data = (ulong)&drv_data_exynos5420 },
+ { .compatible = "samsung,exynos7-wdt", .data = (ulong)&drv_data_exynos7 },
+ { /* sentinel */ }
+};
+
+static inline bool save_reg_from_ofdata(struct udevice *dev, int index, void __iomem **reg)
+{
+ fdt_addr_t addr;
+ fdt_size_t off;
+
+ addr = fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return false;
+
+ *reg = (void __iomem *) addr;
+
+ return true;
+}
+
+static int exynos_wdt_probe(struct udevice *dev)
+{
+ unsigned long wtcon;
+ struct exynos_wdt_priv *wdt = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+ struct udevice *syscon;
+ int err;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ wdt->variant = (void *)dev_get_driver_data(dev);
+ wdt->timeout = EXYNOS_WATCHDOG_DEFAULT_TIME;
+
+ err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+ "samsung,syscon-phandle", &syscon);
+ if (err) {
+ pr_err("unable to find syscon device\n");
+ return err;
+ }
+
+ wdt->pmureg = syscon_get_regmap(syscon);
+ if (!wdt->pmureg) {
+ pr_err("unable to find pmu regmap\n");
+ return -ENODEV;
+ }
+
+ exynos_wdt_stop(dev);
+
+ err = exynos_wdt_mask_and_disable_reset(wdt, false);
+ if (err < 0)
+ return err;
+
+ exynos_wdt_set_heartbeat(dev, wdt->timeout);
+
+ debug("Watchdog probed (timeout=%d sec)\n", wdt->timeout);
+
+ /* print out a statement of readiness */
+
+ wtcon = readl(wdt->wdt_base + EXYNOS_WTCON);
+
+ debug("Watchdog %sactive, reset %sabled, irq %sabled\n",
+ (wtcon & EXYNOS_WTCON_ENABLE) ? "" : "in",
+ (wtcon & EXYNOS_WTCON_RSTEN) ? "en" : "dis",
+ (wtcon & EXYNOS_WTCON_INTEN) ? "en" : "dis");
+
+ return 0;
+}
+
+static int exynos_wdt_ofdata_to_platdata(struct udevice *dev)
+{
+ struct exynos_wdt_priv *priv = dev_get_priv(dev);
+
+ if (!save_reg_from_ofdata(dev, 0, &priv->wdt_base)) {
+ debug("%s: Could not determine EXYNOS wdt IO address\n", __func__);
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(exynos_wdt) = {
+ .name = "exynos_wdt",
+ .id = UCLASS_WDT,
+ .of_match = exynos_wdt_ids,
+ .probe = exynos_wdt_probe,
+ .ops = &exynos_wdt_ops,
+ .priv_auto_alloc_size = sizeof(struct exynos_wdt_priv),
+ .ofdata_to_platdata = exynos_wdt_ofdata_to_platdata,
+};
diff -uNr u-boot-2020.04/drivers/watchdog/Kconfig u-boot-2020.04-exynos_wdt/drivers/watchdog/Kconfig
--- u-boot-2020.04/drivers/watchdog/Kconfig 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/drivers/watchdog/Kconfig 2022-01-02 05:32:57.601020588 +0000
@@ -14,6 +14,7 @@
default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610
default 30000 if ARCH_SOCFPGA
+ default 15000 if ARCH_EXYNOS
default 60000
help
Watchdog timeout in msec
@@ -75,7 +76,7 @@
config WDT_ASPEED
bool "Aspeed ast2400/ast2500 watchdog timer support"
- depends on WDT
+ depends on WDT && ARCH_ASPEED
default y if ARCH_ASPEED
help
Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
@@ -148,12 +149,24 @@
config WDT_ORION
bool "Orion watchdog timer support"
- depends on WDT
+ depends on WDT && ARCH_MVEBU
select CLK
help
Select this to enable Orion watchdog timer, which can be found on some
Marvell Armada chips.
+config WDT_EXYNOS
+ bool "Samsung Exynos watchdog timer support"
+ depends on WDT && ARCH_EXYNOS
+ default y if ARCH_EXYNOS
+ select REGMAP
+ select SYSCON
+ help
+ Select this to enable the Samsung Exynos watchdog
+
+ This provides basic infrastructure to support Samsung Exynos
+ watchdog.
+
config WDT_SANDBOX
bool "Enable Watchdog Timer support for Sandbox"
depends on SANDBOX && WDT
diff -uNr u-boot-2020.04/drivers/watchdog/Makefile u-boot-2020.04-exynos_wdt/drivers/watchdog/Makefile
--- u-boot-2020.04/drivers/watchdog/Makefile 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-exynos_wdt/drivers/watchdog/Makefile 2022-01-02 05:34:50.219933632 +0000
@@ -10,7 +10,6 @@
else
obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o
endif
-obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
@@ -22,6 +21,7 @@
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
+obj-$(CONFIG_WDT_EXYNOS) += exynos_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
u-boot-2020.04-odroid_board_detection_fix.patch 0 → 100644
View file @ 918df1a6
diff -uNr u-boot-2020.04/board/samsung/common/exynos5-dt-types.c u-boot-2020.04-odroid_board_detection_fix/board/samsung/common/exynos5-dt-types.c
--- u-boot-2020.04/board/samsung/common/exynos5-dt-types.c 2020-04-13 15:02:18.000000000 +0000
+++ u-boot-2020.04-odroid_board_detection_fix/board/samsung/common/exynos5-dt-types.c 2021-12-30 08:51:44.151701989 +0000
@@ -41,7 +41,7 @@
{ EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" },
{ EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" },
{ EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1322, "hc1" },
- { EXYNOS5_BOARD_ODROID_HC2_REV01, 1, 1484, "hc1" },
+ { EXYNOS5_BOARD_ODROID_HC2_REV01, 1, 1484, "hc2" },
{ EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" },
};
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