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iWave-SDT
Commit 95c70348 authored by Vladimir Bashkirtsev's avatar Vladimir Bashkirtsev
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iwaveg35m.dts 0 → 100644
View file @ 95c70348
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include "pcw.dtsi"
/ {
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/ram";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &spi0;
};
memory: memory@0 {
compatible = "xlnx,ddr4";
device_type = "memory";
reg = <0x00000000 0x00000000 0x0 0x7ff00000>,
<0x00000008 0x00000000 0x0 0x80000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <0x01>;
#size-cells = <0x00>;
regulator_ssd_vqmmc: regulator_ssd_vqmmc {
compatible = "regulator-gpio";
regulator-name = "ssd_vqmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
gpios-states = <0x00>;
states = <3300000 0x00 1800000 0x01>;
};
regulator_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
off-on-delay-us = <20000>;
};
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
rproc: rproc@70000000 {
no-map;
reg = <0x00 0x70000000 0x00 0x040000>;
};
rpu0vdev0vring0: rpu0vdev0vring0@70040000 {
no-map;
reg = <0x00 0x70040000 0x00 0x004000>;
};
rpu0vdev0vring1: rpu0vdev0vring1@70044000 {
no-map;
reg = <0x00 0x70044000 0x00 0x004000>;
};
rpu0vdev0buffer: rpu0vdev0buffer@70048000 {
no-map;
reg = <0x00 0x70048000 0x00 0x100000>;
};
};
tcm_0a@ffe00000 {
no-map;
reg = <0x00 0xffe00000 0x00 0x10000>;
status = "okay";
compatible = "mmio-sram";
power-domain = <&zynqmp_firmware 0x0f>;
};
tcm_0b@ffe20000 {
no-map;
reg = <0x00 0xffe20000 0x00 0x10000>;
status = "okay";
compatible = "mmio-sram";
power-domain = <&zynqmp_firmware 0x10>;
};
cpus_r5@ff9a0000 {
compatible = "xlnx,zynqmp-r5-remoteproc";
xlnx,cluster-mode = <1>;
ranges;
reg = <0x00 0xff9a0000 0x00 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
#ranges-address-cells = <0x1>;
#ranges-size-cells = <0x1>;
address-map = <0x00000000 &memory 0x00000000 0x80000000>,
<0xf1000000 &amba 0xf1000000 0x0eb00000>,
<0xf9010000 &scugic_0_dist 0xf9010000 0x00010000>;
r5: r5f_0 {
compatible = "arm,cortex-r5";
#address-cells = <2>;
#size-cells = <2>;
ranges;
sram = <0x40 0x41>;
memory-region = <&rproc &rpu0vdev0buffer &rpu0vdev0vring0 &rpu0vdev0vring1>;
power-domain = <&zynqmp_firmware 0x07>;
mboxes = <&ipi1_mailbox_pmu1 0>, <&ipi1_mailbox_pmu1 1>;
mbox-names = "tx", "rx";
};
};
scugic_0_dist: interrupt-controller@f9010000 {
status = "okay";
compatible = "arm,gic-400";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x0 0x10000>,
<0x0 0xf9020000 0x0 0x20000>,
<0x0 0xf9040000 0x0 0x20000>,
<0x0 0xf9060000 0x0 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <1 9 0xf04>;
};
zynqmp_ipi1 {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
xlnx,ipi-id = <7>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ipi1_mailbox_pmu1: mailbox@ff990600 {
reg = <0xff990600 0x20>,
<0xff990620 0x20>,
<0xff9900c0 0x20>,
<0xff9900e0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <1>;
};
};
fmc {
fmc-vadj-millivolt = <1800>;
fmc-prsnt-m2c = <37 0 0>;
fmc-vcc-adj = <37 5 0>;
fmc-vcc-12v = <37 3 0>;
fmc-vcc-3v3 = <37 4 0>;
fmc-pg-c2m = <37 12 0>;
};
fmc_plus {
vadj-millivolt = <1800>;
prsnt-m2c = <37 1 0>;
vcc-adj = <37 6 0>;
vcc-12v = <37 8 0>;
vcc-3v3 = <37 9 0>;
pg-c2m = <37 13 0>;
};
retimer_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
cpu_opp_table {
opp00 {
opp-hz = <0x00 329166666>;
};
opp01 {
opp-hz = <0x00 438888888>;
};
opp02 {
opp-hz = <0x00 658333333>;
};
opp03 {
opp-hz = <0x00 1316666666>;
};
};
};
&gem0 {
local-mac-address = [00 01 02 03 04 05];
phy-handle = <&phy1>; /* u198 */
phy-reset-gpio = <&gpio 42 GPIO_ACTIVE_LOW>;
phy-reset-active-low;
phy-reset-duration = <20>;
phy1: phy@1 {
reg = <1>;
compatible = "ethernet-phy-id004d.d074";
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <1>;
ti,rxctrl-strap-worka;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
at803x,vddio-1p8v;
interrupt-parent = <&gpio>;
interrupts = <12 8>;
};
};
&i2c0 {
status = "okay";
da9062@58 {
compatible = "dlg,da9062";
reg = <0x58>;
rtc {
compatible = "dlg,da9062-rtc";
};
gpio {
compatible = "dlg,da9062-gpio";
};
};
typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
fcs,int_n = <0x15 0x4e 0x08>;
fcs,cc = <0x15 0x4f 0x00>;
fcs,power_en = <0x15 0x19 0x00>;
vbus-supply = <&regulator_vbus>;
status = "okay";
};
hdmi-retimer@5b {
status = "okay";
compatible = "ti,dp159";
reg = <0x5b>;
#address-cells = <0x01>;
#size-cells = <0x00>;
#clock-cells = <0x00>;
};
msd9546@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
status = "okay";
#address-cells = <0x01>;
#size-cells = <0x00>;
i2c@0 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
gpio@23 {
compatible = "ti,tca9535";
reg = <0x23>;
#gpio-cells = <0x02>;
gpio-controller;
};
};
i2c@1 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x01>;
};
i2c@2 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x02>;
gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
#gpio-cells = <0x02>;
gpio-controller;
};
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
#gpio-cells = <0x02>;
gpio-controller;
};
};
i2c@3 {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x03>;
eeprom@51 {
compatible = "atmel,24c32";
reg = <0x51>;
pagesize = <0x20>;
address-width = <16>;
size = <0x8000>;
};
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <0x20>;
address-width = <16>;
size = <0x8000>;
};
};
};
};
&gic {
status = "okay";
};
&sdhci0 {
bus-width = <8>;
};
&sdhci1 {
clock-frequency = <200000000>;
bus-width = <4>;
xlnx,has-cd = <1>;
vqmmc-supply = <&regulator_ssd_vqmmc>;
};
&spi0 {
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0x00>;
spi-max-frequency = <100000000>;
};
};
&usb0 {
xlnx,usb-reset = <50000000>;
};
&dwc3_0 {
snps,resume-hs-terminations;
dr_mode = "otg";
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
};
&watchdog0 {
timeout-sec = <70>;
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&video_clk {
clock-frequency = <33333000>;
};
&amba {
interrupt-multiplex {
status = "disabled";
};
};
pcw.dtsi 0 → 100644
View file @ 95c70348
&fclk0 {
status = "okay";
};
&gic {
num_cpus = <2>;
num_interrupts = <96>;
};
&lpd_dma_chan1 {
status = "okay";
};
&lpd_dma_chan2 {
status = "okay";
};
&lpd_dma_chan3 {
status = "okay";
};
&lpd_dma_chan4 {
status = "okay";
};
&lpd_dma_chan5 {
status = "okay";
};
&lpd_dma_chan6 {
status = "okay";
};
&lpd_dma_chan7 {
status = "okay";
};
&lpd_dma_chan8 {
status = "okay";
};
&xilinx_ams {
status = "okay";
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&cci {
status = "okay";
};
&zynqmp_dpsub {
phy-names = "dp-phy0";
phys = <&psgtr 1 6 0 1>;
status = "okay";
xlnx,max-lanes = <1>;
};
&zynqmp_dpdma {
status = "okay";
};
&gem0 {
phy-mode = "rgmii-id";
status = "okay";
xlnx,ptp-enet-clock = <0x0>;
};
&gem3 {
phy-mode = "rgmii-id";
status = "okay";
xlnx,ptp-enet-clock = <0x0>;
};
&fpd_dma_chan1 {
status = "okay";
};
&fpd_dma_chan2 {
status = "okay";
};
&fpd_dma_chan3 {
status = "okay";
};
&fpd_dma_chan4 {
status = "okay";
};
&fpd_dma_chan5 {
status = "okay";
};
&fpd_dma_chan6 {
status = "okay";
};
&fpd_dma_chan7 {
status = "okay";
};
&fpd_dma_chan8 {
status = "okay";
};
&gpio {
emio-gpio-width = <32>;
gpio-mask-high = <0x0>;
gpio-mask-low = <0x5600>;
status = "okay";
};
&gpu {
status = "okay";
xlnx,tz-nonsecure = <0x1>;
};
&i2c0 {
status = "okay";
};
&pcie {
status = "okay";
xlnx,bar0-enable = <0x0>;
xlnx,bar1-enable = <0x0>;
xlnx,bar2-enable = <0x0>;
xlnx,bar3-enable = <0x0>;
xlnx,bar4-enable = <0x0>;
xlnx,bar5-enable = <0x0>;
xlnx,pcie-mode = "Root Port";
xlnx,tz-nonsecure = <0x0>;
};
&rtc {
status = "okay";
};
&sata {
status = "okay";
xlnx,tz-nonsecure-sata0 = <0x0>;
xlnx,tz-nonsecure-sata1 = <0x0>;
};
&sdhci0 {
clock-frequency = <187500000>;
status = "okay";
xlnx,mio-bank = <0x0>;
};
&sdhci1 {
clock-frequency = <187500000>;
status = "okay";
xlnx,mio-bank = <0x1>;
};
&psgtr {
status = "okay";
};
&spi0 {
is-decoded-cs = <0>;
num-cs = <1>;
status = "okay";
};
&ttc0 {
status = "okay";
};
&ttc1 {
status = "okay";
};
&ttc2 {
status = "okay";
};
&ttc3 {
status = "okay";
};
&uart0 {
cts-override ;
device_type = "serial";
port-number = <0>;
status = "okay";
u-boot,dm-pre-reloc ;
};
&uart1 {
cts-override ;
device_type = "serial";
port-number = <1>;
status = "okay";
u-boot,dm-pre-reloc ;
};
&usb0 {
status = "okay";
xlnx,tz-nonsecure = <0x1>;
xlnx,usb-polarity = <0x0>;
xlnx,usb-reset-io = <0x2a>;
xlnx,usb-reset-mode = <0x1>;
};
&dwc3_0 {
status = "okay";
};
&lpd_watchdog {
status = "okay";
};
&watchdog0 {
status = "okay";
};
&pss_ref_clk {
clock-frequency = <33333333>;
};
&video_clk {
clock-frequency = <33333000>;
};
&ams_ps {
status = "okay";
};
&ams_pl {
status = "okay";
};
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&zynqmp_dp_snd_card0 {
status = "okay";
};
&zynqmp_dp_snd_codec0 {
status = "okay";
};
zynqmp-clk-ccf.dtsi 0 → 100644
View file @ 95c70348
// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
fclk0: fclk0 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <&zynqmp_clk PL0_REF>;
};
fclk1: fclk1 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <&zynqmp_clk PL1_REF>;
};
fclk2: fclk2 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <&zynqmp_clk PL2_REF>;
};
fclk3: fclk3 {
status = "okay";
compatible = "xlnx,fclk";
clocks = <&zynqmp_clk PL3_REF>;
};
pss_ref_clk: pss_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
video_clk: video_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
pss_alt_ref_clk: pss_alt_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gt_crx_ref_clk: gt_crx_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
};
aux_ref_clk: aux_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&zynqmp_firmware {
zynqmp_clk: clock-controller {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
<&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
"aux_ref_clk", "gt_crx_ref_clk";
};
};
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&can1 {
clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&cpu0 {
clocks = <&zynqmp_clk ACPU>;
};
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan2 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan3 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan4 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan5 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan6 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan7 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan8 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gpu {
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan2 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan3 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan4 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan5 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan6 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan7 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan8 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&nand0 {
clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gem0 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
assigned-clocks = <&zynqmp_clk GEM_TSU>;
};
&gpio {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&i2c0 {
clocks = <&zynqmp_clk I2C0_REF>;
};
&i2c1 {
clocks = <&zynqmp_clk I2C1_REF>;
};
&perf_monitor_ocm {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&perf_monitor_ddr {
clocks = <&zynqmp_clk TOPSW_LSBUS>;
};
&perf_monitor_cci {
clocks = <&zynqmp_clk TOPSW_LSBUS>;
};
&perf_monitor_lpd {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&pcie {
clocks = <&zynqmp_clk PCIE_REF>;
};
&qspi {
clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&sata {
clocks = <&zynqmp_clk SATA_REF>;
};
&sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO0_REF>;
};
&sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
assigned-clocks = <&zynqmp_clk SDIO1_REF>;
};
&spi0 {
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi1 {
clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&ttc0 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc1 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc2 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc3 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_0 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&dwc3_1 {
clocks = <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};
&lpd_watchdog {
clocks = <&zynqmp_clk LPD_WDT>;
};
&xilinx_ams {
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
assigned-clocks = <&zynqmp_clk DP_STC_REF>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
};
&zynqmp_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
zynqmp.dtsi 0 → 100644
View file @ 95c70348
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