Fixed PLL1 setup on Oranges

Makefile

 opiplus2e: opiplus2e-boot-cmd opiplus2e-fw_env.config
 	tar xf u-boot-2020.04.tar.bz2
+	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi_env_in_mmc0.patch
 	$(MAKE) -C u-boot-2020.04 orangepi_plus2e_defconfig
@@ -42,6 +43,7 @@ export FW_ENV_OPIPLUS2E
 
 opiplus2e-mender: opiplus2e-boot-cmd-mender opiplus2e-fw_env.config-mender
 	tar xf u-boot-2020.04.tar.bz2
+	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-mender.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi_wdt.patch
@@ -95,6 +97,7 @@ export FW_ENV_OPIPLUS2E_MENDER
 
 opipcplus: opipcplus-boot-cmd opipcplus-fw_env.config
 	tar xf u-boot-2020.04.tar.bz2
+	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi_env_in_mmc0.patch
 	$(MAKE) -C u-boot-2020.04 orangepi_pc_plus_defconfig
@@ -137,6 +140,7 @@ export FW_ENV_OPIPCPLUS
 
 opipcplus-mender: opipcplus-boot-cmd-mender opipcplus-fw_env.config-mender
 	tar xf u-boot-2020.04.tar.bz2
+	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-serial-number-fix.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-mender.patch
 	patch -Np1 -d u-boot-2020.04 < u-boot-2020.04-sunxi_wdt.patch

u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch

+diff -uNr u-boot-2020.04/arch/arm/mach-sunxi/clock_sun6i.c u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers/arch/arm/mach-sunxi/clock_sun6i.c
+--- u-boot-2020.04/arch/arm/mach-sunxi/clock_sun6i.c	2020-04-14 00:32:18.000000000 +0930
++++ u-boot-2020.04-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers/arch/arm/mach-sunxi/clock_sun6i.c	2021-05-10 23:26:33.607420988 +0930
+@@ -115,11 +115,10 @@
+ 	int k = 1;
+ 	int m = 1;
+ 
+-	if (clk > 1152000000) {
+-		k = 2;
+-	} else if (clk > 768000000) {
++	if (clk >= 1368000000) {
+ 		k = 4;
+-		m = 2;
++	} else if (clk >= 768000000) {
++		k = 2;
+ 	}
+ 
+ 	/* Switch to 24MHz clock while changing PLL1 */